Dynamic partitioning of processing and memory resources in embedded MPSoC architectures

Xue, Liping; Öztürk, Özcan; Li, F.; Kandemir, Mahmut; Kolcu, I.

doi:10.1109/date.2006.244044

Cited by 21 publications

(26 citation statements)

References 10 publications

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“…As mentioned earlier, we compare our approach to the effective technique in [31]. Testing our techniques is not an easy task as this article assumes that applications can get into the system at random times in contrast to predefined times.…”

Section: Resultsmentioning

confidence: 99%

“…- [31]: This is the approach presented in [31]. In this approach, the authors divide the available resources carefully among the applications to reduce the run time.…”

Section: Resultsmentioning

confidence: 99%

“…The closest to what we are doing is the technique presented in [31]. Hence, we implemented the following two techniques and performed our experiments and compared the results:…”

Section: Resultsmentioning

confidence: 99%

“…Other works [23,24,25,26,27,28,29,30] have studied issues related to task scheduling/allocation and memory partitioning on multiprocessor systems. Xue et al [31] proposed a dynamic resource partitioner for embedded applications in an MPSoC. Their proposed approach partitions the resources in a manner proportional to the requirements of each application.…”

Section: Related Workmentioning

confidence: 99%

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An Effective Resource Partitioning Heuristic for Embedded Applications on an MPSoC

Salamy¹,

Sopeju²

2014

IJCA

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As the utilization of multiprocessors system-on-chip (MPSoC) is becoming ubiquitous, demands for effective allocation and scheduling techniques are needed more than ever to harness the power of MPSoCs. An MPSoC is a system consisting of multiple heterogeneous processing cores, memory hierarchies, and communication infrastructure to effectively overcome the power and clock constraints from single core architectures. MPSoCs provide the performance demanded by embedded applications especially real-time multimedia applications. This article presents effective techniques to partitioning the processing cores and memory budget in an MPSoC among multiple embedded applications possibly entering the system at different times. The proposed framework will study the structure of each application and predict the possible reduction in schedule time if more processors and/or memory budget are assigned to this application. The objective is to fairly divide the resources such that the schedule times for the applications are minimized. Results on different embedded applications workloads and under different system resources show the effectiveness of our techniques that were able to reduce the cycle count by 10.2 % on average compared to an effective technique in the literature.

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Section: Resultsmentioning

confidence: 99%

“…- [31]: This is the approach presented in [31]. In this approach, the authors divide the available resources carefully among the applications to reduce the run time.…”

Section: Resultsmentioning

confidence: 99%

“…The closest to what we are doing is the technique presented in [31]. Hence, we implemented the following two techniques and performed our experiments and compared the results:…”

Section: Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

An Effective Resource Partitioning Heuristic for Embedded Applications on an MPSoC

Salamy¹,

Sopeju²

2014

IJCA

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show abstract

“…Regarding memory partitioning, in [10], Xue explores a proactive resource partitioning scheme for parallel applications simultaneously exercising the same MPSoC system. His work combined memory partitioning and processor partitioning and revealed that both are very important to obtain best system performance.…”

Section: Related Workmentioning

confidence: 99%

Run-Time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips

Chen

Jantsch

et al. 2010

2010 3rd International Symposium on Parallel Architectures, Algorithms and Programming

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Abstract-On multi-core Network-on-Chips (NoCs), memories are preferably distributed and supporting Distributed Shared Memory (DSM) is essential for the sake of reusing huge amount of legacy code and easy programming. However, the DSM organization imports the inherent overhead of translating virtual memory addresses into physical memory addresses, resulting in negative performance. We observe that, in parallel applications, different data have different properties (private or shared). For the private data accesses, it's unnecessary to perform Virtual-to-Physical address translations. Even for the same datum, its property may be changeable in different phases of the program execution. Therefore, this paper focuses on decreasing the overhead of Virtual-to-Physical address translation and hence improving the system performance by introducing hybrid DSM organization and supporting run-time partitioning according to the data property. The hybrid DSM organization aims at supporting fast and physical memory accesses for private data and maintaining a global and single virtual memory space for shared data. Based on the data property of parallel applications, the run-time partitioning supports changing the hybrid DSM organization during the program execution. It ensures fast physical memory addressing on private data and conventional virtual memory addressing on shared data, improving the performance of the entire system by reducing virtual-to-physical address translation overhead as much as possible. We formulate the run-time partitioning of hybrid DSM organization in order to analyze its performance. A real DSM based multi-core NoC platform is also constructed. The experimental results of real applications show that the hybrid DSM organization with run-time partitioning demonstrates performance advantage over the conventional DSM counterpart. The percentage of performance improvement depends on problem size, way of data partitioning and computation/communication ratio of parallel applications, network size of the system, etc. In our experiments, the maximal improvement is 34.42%, the minimal improvement 3.68%.

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Embedded Software Design and Programming of Multiprocessor System-on-Chip

Popovici

Rousseau

Jerraya

et al. 2010

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Dynamic partitioning of processing and memory resources in embedded MPSoC architectures

Cited by 21 publications

References 10 publications

An Effective Resource Partitioning Heuristic for Embedded Applications on an MPSoC

An Effective Resource Partitioning Heuristic for Embedded Applications on an MPSoC

Run-Time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips

Embedded Software Design and Programming of Multiprocessor System-on-Chip

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