Dynamic partial FPGA reconfiguration in space applications

Abstract

Design and implementation of hardware mock-up of high performance system for general avionics testing in reconfigurable FPGAs. Strong emphasis is put on exploiting dynamic partial reconfiguration capability as a method for functionality multiplexing and fault mitigation. Additionally, dynamic reconfiguration can be used for fault injection which makes Single Event Upset in configuration memory simulation possible. LEON3 processors are used to create an avionic systems test-bed, for testing the mock-ups of real system flight software and testing dynamic full and partial reconfiguration. Experiments with different means of reconfiguration are performed to measure reconfiguration times and stability of software. Several solutions for whole system reconfiguration controller have been implemented and tested.

Research on reconfiguration technology based on SOPC for PXI instrument

“…The results indicate that the protocol is consist of 3 parts: 1chanel of synchronous RS-485 reception-transmission for fixed time, 1chanel of asynchronous RS-422, 1chanel of RS-485 continuous reception. In addition to the information mentioned above, the results also indicate the dynamic reconfiguration's time spending depends on the size of dynamically partial region [8] [9] . The bigger the data is, the longer time will be spent.…”