Dynamic off-state TDDB of ultra short channel HKMG nFETS and its implications on CMOS logic reliability

Kupke, S.; Knebel, S.; Rahman, Saifur; Slesazeck, Stefan; Mikolajick, Thomas; Agaiby, Rimoon; Trentzsch, Martin

doi:10.1109/irps.2014.6860661

Cited by 16 publications

(1 citation statement)

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“…a continuous change of the polarization state, results in a degradation and consequent reduction of the MW. In contrast the unipolar stress does not influence the MW significantly [59,81,82]. Leakage current defect spectroscopy proved that independent of the polarity of the unipolar stress pulses, both leakage current and memory window stayed constant.…”

Section: Fatiguementioning

confidence: 99%

A computational study of hafnia-based ferroelectric memories: from ab initio via physical modeling to circuit models of ferroelectric device

et al. 2017

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Abstract. The discovery of ferroelectric properties of binary oxides revitalized the interest in ferroelectrics and bridged the scaling gap between the state-of-the-art semiconductor technology and ferroelectric memories. However, before hitting the markets, the origin of ferroelectricity and in-depth studies of device characteristics are needed. Establishing a correlation between the performance of the device and underlying physical mechanisms is the first step toward understanding the device and engineering guidelines for a novel, superior device. Therefore, in this paper a holistic modeling approaches which lead to a better understanding of ferroelectric memories based on hafnium and zirconium oxide is addressed. Starting from describing the stabilization of the ferroelectric phase within the binary oxides via physical modeling the physical mechanisms of the ferroelectric devices are reviewed. Besides, limitations and modeling of the multi-level operation and switching kinetics of ultimately scaled devices as well as the necessity for Landau-Khalatnikov approach are discussed. Furthermore, a device level model of ferroelectric memory devices that can be used to study the array implementation and their operational schemes are addressed. Finally, a circuit model of the ferroelectric memory device is presented and potential further applications of ferroelectric devices are outlined.

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Section: Fatiguementioning

confidence: 99%