Dynamic noise margins of MOS logic gates

Żurada, Jacek M.; Joo, Y.S.; Bell, S.V.

doi:10.1109/iscas.1989.100557

Cited by 22 publications

(10 citation statements)

References 2 publications

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“…Lostroh introduced the noise immunity curve (NIC) in his groundbreaking paper from 1979 [7], presenting a shmoo plot showing regions of failure and success for a logic gate in the presence of a trapezoidal noise pulse of a given amplitude and duration. Zurada [28] displayed dynamic (AC) VTCs for logic gates, which led to Ding's definition of maximum square based dynamic noise margins [4]. However, these definitions do not sufficiently capture the dynamic requirements of SRAM stability, leading to Dong's definition of DNM [5], as the margin of time between the applied pulse and the minimum time to cause a state flip (in write) or maintain data retention (in read).…”

Section: Sram Stability Analysismentioning

confidence: 99%

A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs

Teman

Visotsky²

2015

IEEE Trans. VLSI Syst.

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Abstract-As memory density continues to grow in modern systems, accurate analysis of SRAM stability is increasingly important to ensure high yields. Traditional static noise margin metrics fail to capture the dynamic characteristics of SRAM behavior, leading to expensive over-design and disastrous under-design. One of the central components of more accurate dynamic stability analysis is the separatrix; however, its straightforward extraction is extremely time-consuming, and efficient methods are either non-accurate or extremely difficult to implement. In this paper, we propose a novel algorithm for fast separatrix tracing of any given SRAM topology, designed with industry standard transistor models in nano-scaled technologies. The proposed algorithm is applied to both standard 6T SRAM bitcells, as well as previously proposed alternative sub-threshold bitcells, providing up to three orders-of-magnitude speedup, as compared to brute force methods. In addition, for the first time, statistical Monte Carlo separatrix distributions are plotted.

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Section: Sram Stability Analysismentioning

confidence: 99%

A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs

Teman

Visotsky²

2015

IEEE Trans. VLSI Syst.

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“…For very long noise pulses the noise margins are determined by static noise analysis, but for short pulses the noise margins increase. Dynamic noise analysis provides the noise margin for noise pulses [11]. For shorter pulses the margin is higher while for longer pulses the dynamic noise margin tends to converge with the static noise margin.…”

Section: Dynamic Noise Marginmentioning

confidence: 99%

A novel and fast method for characterizing noise based PCMOS circuits

Singh

Mandavalli

Mooney

et al. 2011

2011 3rd Asia Symposium on Quality Electronic Design (ASQED)

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Quick and accurate error-rate prediction of Probabilistic CMOS (PCMOS) circuits is crucial for their systematic design and performance evaluation. While still in early stage of research, PCMOS has shown potential to drastically reduce energy consumption at a cost of increased errors. Recently, a methodology has been proposed which could predict the error-rates of cascade structures of blocks in PCMOS. It requires error-rates of unique blocks to predict the error-rates of a multi-block cascade structure. The "Three stage model," which accounts for different noise filtering for different paths in a circuit, has been proposed to characterize unique blocks. While the results obtained from the three stage model produced accurate error-rates for a multi-block cascade structure, the procedure for its characterization is computationally expensive. In this paper, we propose a new method for characterizing the three stage model that not only provides accurate results but is also computationally cheap.

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“…Pulse-noise amplitudes are allowed to be higher than static noise margins would allow, depending on the shape of the pulse. These dynamic noise margins are very dependent on the exact time-domain characteristics of the pulse noise [17]. Reference [18] introduces the idea of noise tolerance to define the point at which a symmetric noise pulse shows amplification to the output.…”

Section: B Noise Stabilitymentioning

confidence: 99%

“…Let be the binary variable indicating whether the given secondary net driver is switching, and let be the number of secondary nets. The problem is then to maximize (17) such that the following constraints can be satisfied for all :…”

Section: B Global Analysis-global Harmonymentioning

confidence: 99%

Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits

Singh¹

2009

Signal Integrity Effects in Custom IC and ASIC Designs

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Abstract-As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of very large scale integrated (VLSI) systems. A metric for noise immunity is defined, and a static noise analysis methodology based on this noise-stability metric is introduced to demonstrate how noise can be analyzed systematically on a full-chip basis using simulationbased transistor-level analysis. We then describe Harmony, a two-level (macro and global) hierarchical implementation of static noise analysis. At the macro level, simplified interconnect models and timing assumptions guide efficient analysis. The global level involves a careful combination of static noise analysis, static timing analysis, and detailed interconnect macromodels based on reduced-order modeling techniques. We describe how the interconnect macromodels are practically employed to perform coupling analysis and how timing constraints can be used to limit pessimism in the analysis.Index Terms-Deep-submicron IC's, interconnect coupling, signal integrity, static noise analysis.

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Dynamic noise margins of MOS logic gates

Cited by 22 publications

References 2 publications

A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs

A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs

A novel and fast method for characterizing noise based PCMOS circuits

Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits

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