Dynamic Multiway Segment Tree for IP Lookups and the Fast Pipelined Search Engine

Abstract

A dynamic multiway segment tree (DMST) is proposed for IP lookups in this paper. DMST is designed for dynamic routing tables that can dynamically insert and delete prefixes. DMST is implemented as a B-tree that has all distinct endpoints of ranges as its keys. The complexities of search, insertion, deletion, and memory requirement are the same as the existing multiway range tree (MRT) and prefix in B-tree (PIBT) for prefixes. In addition, a pipelined DMST search engine is proposed to further speed up the search operations. The proposed pipelined DMST search engine uses off-chip SRAMs instead of on-chip SRAMs because the capacity of the latter is too small to hold large routing tables and the cost of the latter is too expensive. By utilizing current FPGA and off-chip SRAM technologies, our proposed 5-stage pipelined search engine can achieve the worst-case throughputs of 33.3 and 41.7 million packets per second (Mpps) with 144-bit and 288-bit wide SRAM blocks, respectively. Furthermore, a straightforward extension of the pipelined search engine with multiple independent off-chip SRAMs can achieve the throughput of 200 Mpps which is equivalent to 102 Gbps for minimal Ethernet packets of size 64 bytes.

Bit-Shuffled Trie: IP Lookup with Multi-Level Index Tables

“…of prefixes Bytes/prefix Next-hop data Eatherton [3] 19K to 41K 11 to 13 not included Lunteren [6] 72.8K 6.5 8-bit/prefix Pao [9] 41.4K 17.6 8-bit/prefix Taylor [17] 27.7K 7.3 8-bit/prefix Chang [2] 163.5K 8.7 to 9.4 8-bit/prefix Song [12] 250K 22 8-bit/prefix Sourdis [14] 270K 3 not included Sun [16] 18K to 161K 2.6 to 3 not included Bit-shuffled trie 321K 2.8 not included…”

“…Hence, there have been active researches on algorithmic RAM-based IP lookup methods. There are 3 major approaches for algorithmic IP lookup methods, namely, trie-based methods [3,5,6,7,9,13,17], range search methods [2,14,16], and hashing-based methods [1,12]. In this paper, we shall present the design of a hardware IP lookup engine using multi-level index tables, where the index tables are derived based on a modified binary-trie structure called the bit-shuffled trie.…”

An Efficient Update Mechanism for GPU-Based IP Lookup Engine Using Threaded Segment Tree

“…Some of its extensions have been already used in IP lookup [14] and packet classifying [15]. They all transform prefixes into segments in a straightforward way.…”

Bit-shuffled trie

“…We evaluate the memory cost of the proposed method using a real-life IPv4 routing [1] 163.5K 8.7 to 9.4 Eatherton [2] 19K to 41K 11 to 13 Lunteren [4] 72.8K 6.5 Pao [5] 41.4K 17.6 Sourdis [6] 275K 3 Bit-shuffled trie 321K 2.6…”