Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors

Abstract

Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. However, these mobile processors are also expected to be compact, ultra-portable, and provide an always-on, continuous data access paradigm necessitating a low-power design. As mobile processors increasingly begin to leverage multicore functionality, the power consumption incurred from maintaining coherence between local caches due to bus snooping becomes more prevalent. This paper explores a novel approach to mitigating multi-core processor power consumption in mobile smartphones. By using dynamic application memory behavior, one can intelligently target adjustments in the cache coherency protocol to help reduce the overhead of maintaining consistency when the benefits of multi-core shared cache coherence are muted. On the other hand, by utilizing a fine-grained approach, the proposed architecture can still respond to and enable the benefits of hardware cache coherence in situations where the performance improvements greatly outweigh the associated energy costs. The simulation results show appreciable reductions in overall cache power consumption, with negligible impact to overall execution time.

Design and Implementation of a Chip Multiprocessor with an Efficient Multilevel Cache System

“…Some of the proposed CMP designs implement multilevel cache systems with private hierarchy [7]. Other proposed designs implement systems with private L1 caches and shared L2 caches [9][10][11]. Other designs implement cache systems with two private levels and a third shared level among all cores [6,12].…”

“…However, other proposed papers in this field say that write-through protocol perform well to ensure data consistent with drawback of higher write traffic as compared to write-back, since writethrough requires synchronous updates for every write [14,16]. [9] explores a novel approach to mitigating multicore power consumption by using dynamic application memory behavior. The main notice is that using only write-through policy causes more contention on the bus.…”

Design and Implementation of a Simple Cache Simulator in Java to Investigate MESI and MOESI Coherency Protocols

“…In MCSoC, the most common cache coherency protocol used is the MESI protocol. But since the MESI protocol is most commonly used in MCSoC system, that may give rise to bandwidth loss over snoopy bus, and for that reason, Bournoutian [9] of the University of California, San Diego, proposed in 2011, a powerful optimized mixture of write-back and write-through MESI protocol with an extra hardware modification in order to increase performance and power efficiency of the mobile processors. In the proposal, write-back is used when there are numerous updates on the cache line and that gives more performance, whereas write-through is used in order to achieve power optimization.…”

Construction of GCCFG for inter-procedural optimizations in software managed manycore (SMM) architectures

“…Experts believe that coherent cache architectures will not scale to hundreds and thousands of cores [11,12,16,25], not only because the hardware overheads of providing coherency increases rapidly with core count, but also because caches consume a lot of power. One promising option for a more powerefficient and scalable memory hierarchy is to use raw, "uncached" memory (commonly known as Scratch Pad Memory or SPM) in the cores.…”