Dynamic Model of Switched-Capacitor DC–DC Converters in the Slow-Switching Limit Including Charge Reusing

Ferro, E.; Brea, V.M.; López, P.; Cabello, D.

doi:10.1109/tpel.2016.2607800

Cited by 14 publications

(7 citation statements)

References 42 publications

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“…The MPPT block is designed to meet the maximum PMU efficiency adjusting both the gain and the capacitance per stage of the main charge pump and the clock signals' frequency of both charge pumps. A joint analytical model of photodiode and charge pump developed by the authors in [18], [27] is used to predict the photodiode response for every working region, searching for the maximum load (I L MAX ) which yields 1.1 V at the PMU output during the design phase. So, our MPPT method can be regarded as a lookup table defined in the design phase.…”

Section: A Mppt Architecturementioning

confidence: 99%

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Micro-Energy Harvesting System Including a PMU and a Solar Cell on the Same Substrate With Cold Startup From 2.38 nW and Input Power Range up to 10 $\mu$W Using Continuous MPPT

Ferro

Brea

López

et al. 2019

IEEE Trans. Power Electron.

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This paper presents a Power Management Unit (PMU) powered by a 1 mm 2 solar cell on the same substrate to rise up the harvested voltage above 1.1 V. The on-chip solar cell and the PMU are fabricated in standard 0.18 μm CMOS technology achieving a form factor of 1.575 mm 2. The PMU is able to start up from a harvested power of 2.38 nW without any external kick off or control signal. The PMU features a continuous and two-dimensional Maximum Power Point Tracking (MPPT) working in open-loop mode to handle a harvested power range from nW to μW, by modifying both the charge pump topology and the switching frequency. The MPPT is based on four voltage level detectors that define five working regions depending on the illumination and on a self-tuning reference current for a fine adjustment of the switching frequency. The chip also includes an auxiliary charge pump to generate the voltage level necessary for the control circuit, implemented as a Pelliconi charge pump of 8 stages with NMOS transistors in Pwell as diodes. A Dickson charge pump with transmission gates as switches and with variable gain and capacitance per stage is also designed as the main charge pump. Finally, two relaxation oscillators are implemented to drive both charge pumps. This paper is accompanied by a video file demonstrating the PMU operation by powering an off-chip NAND gate.

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Section: A Mppt Architecturementioning

confidence: 99%

“…6 depicts the schematic of the main charge pump. The gain and the capacitance per stage were designed with the circuit models introduced by the authors in [18], [27]. Table II summarizes the gain and the capacitance per stage of the main charge pump for the different working regions.…”

Section: A Main Charge Pumpmentioning

confidence: 99%

Micro-Energy Harvesting System Including a PMU and a Solar Cell on the Same Substrate With Cold Startup From 2.38 nW and Input Power Range up to 10 $\mu$W Using Continuous MPPT

Ferro

Brea

López

et al. 2019

IEEE Trans. Power Electron.

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“…Among the papers dealing with the dynamic modeling of CPs, in the following, we consider the methodology originally presented in Tanzawa and Tanaka …”

Section: The Proposed Design Strategymentioning

confidence: 99%

“…Among the papers dealing with the dynamic modeling of CPs, [16][17][18][19][20] in the following, we consider the methodology originally presented in Tanzawa and Tanaka. 19 The total amount of input charge during the transient of a N-stages Dickson CP is due to the charge stored in the output capacitor, C L , and the sum of the charge stored in the odd-order, C 2k-1 , and the even-order, C 2k , capacitors, during a generic jth semi-period, whose expressions are, respectively, given by 19,20…”

Section: The Proposed Design Strategymentioning

confidence: 99%

Linear distribution of capacitance in Dickson charge pumps to reduce rise time

Ballo

Grasso

Palumbo

et al. 2020

Circuit Theory & Apps

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Summary This paper introduces a design strategy to reduce rise time of charge pumps maintaining equal the silicon area, which is effective when the load capacitance is lower than the total charge pump capacitance. The strategy relies on an unconventional pumping capacitors sizing, which set them not equal and follows a linear distribution. The approach is based on a theoretical analysis and is validated through post‐layout simulations using a 130‐nm complementary metal‐oxide semiconductor (CMOS) standard technology. The simulations demonstrate the advantages of the proposed design strategy and the accuracy of the theory.

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“…The proposed architecture is based on switched capacitor (SC) converter [81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98] stages that can be easily integrated in silicon since they are characterized by the use of only capacitors and switches. The switches are realized in silicon through MOS transistors.…”

Section: Models Of the Multi-output Switched Capacitor Convertermentioning

confidence: 99%

Fully-Integrated Converter for Low-Cost and Low-Size Power Supply in Internet-of-Things Applications

Gutiérrez¹

2017

Electronics

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Abstract:The paper presents a fully-integrated and universal DC/DC converter to minimize cost and size of power supply systems in wireless nodes for Internet-of-Things (IoT) applications. The proposed converter avoids the use of inductors and is made by a cascade of switching capacitor stages, implementing both step-down and step-up converting ratios, which regulate input sources from 1 V to 60 V to a voltage of about 4 V. Multiple linear regulators are placed at the end of the cascade to provide multiple and stable output voltages for loads such as memories, sensors, processors, wireless transceivers. The multi-output power converter has been integrated in a Bipolar-CMOS-DMOS (BCD) 180 nm technology. As case study, the generation of 3 output voltages has been considered (3 V, 2.7 V, and 1.65 V with load current requirements of 0.3 A, 0.3 A, and 0.12 A, respectively). Thanks to the adoption of a high switching frequency, up to 5 MHz, the only needed passive components are flying capacitors, whose size is below 10 nF, and buffer capacitors, whose size is below 100 nF. These capacitors can be integrated on top of the chip die, creating a 3D structure. This way, the size of the power management unit for IoT and CPS nodes is limited at 18 mm 2 . The proposed converter can also be used with changing input power sources, like power harvesting systems and/or very disturbed power supplies.

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Dynamic Model of Switched-Capacitor DC–DC Converters in the Slow-Switching Limit Including Charge Reusing

Cited by 14 publications

References 42 publications

Micro-Energy Harvesting System Including a PMU and a Solar Cell on the Same Substrate With Cold Startup From 2.38 nW and Input Power Range up to 10 $\mu$W Using Continuous MPPT

Micro-Energy Harvesting System Including a PMU and a Solar Cell on the Same Substrate With Cold Startup From 2.38 nW and Input Power Range up to 10 $\mu$W Using Continuous MPPT

Linear distribution of capacitance in Dickson charge pumps to reduce rise time

Fully-Integrated Converter for Low-Cost and Low-Size Power Supply in Internet-of-Things Applications

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