Dynamic Fault Tree Analysis and Risk Mitigation Strategies of Data Communication System via Statistical Model Checking

Samadi, Ashkan; Ammar, Marwan; Mohamed, Otmane Aït

doi:10.1109/newcas50681.2021.9462743

Cited by 2 publications

(3 citation statements)

References 9 publications

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“…The third difference is that the proposed method is friendly to hardware designers and verifiers. Samadi's method involved creating a library to transform the DUT to FT models [31]. It is hard to create such a library.…”

Section: Discussionmentioning

confidence: 99%

“…The last difference is that we categorize faults according to fault effects. Other works use formal verification to find critical faults [31] or structurally safe faults [35]. Our proposed method can find both; it can find faults causing nothing, and faults causing SDCs/crashes/hangs.…”

Section: Discussionmentioning

confidence: 99%

“…Yamaguchi developed a library of formal specifications at both the system level and subsystem level for autonomous system verification [30]. Samadi used Fault Tree Analysis (FTA) to evaluate system reliability [31].…”

Section: Related Workmentioning

confidence: 99%

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Using Formal Methods to Evaluate Hardware Reliability in the Presence of Soft Errors

Xue

Zwoliński

2022

2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)

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Reliability has been a major concern in embedded systems. Higher transistor density and lower voltage supply increase the vulnerability of embedded systems to soft errors. A Single Event Upset (SEU), which is also called a soft error, can reverse a bit in a sequential element, resulting in a system failure. Simulation-based fault injection has been widely used to evaluate reliability, as suggested by ISO26262. However, it is practically impossible to test all faults for a complex design. Random fault injection is a compromise that reduces accuracy and fault coverage. Formal verification is an alternative approach. In this paper, we use formal verification, in the form of model checking, to evaluate the hardware reliability of a RISC-V Ibex Core in the presence of soft errors. Backward tracing is performed to identify and categorize faults according to their effects (no effect, Silent Data Corruption, crashes, and hangs). By using formal verification, the entire state space and fault list can be exhaustively explored. It is found that misaligned instructions can amplify fault effects. It is also found that some bits are more vulnerable to SEUs than others. In general, most of the bits in the Ibex Core are vulnerable to Silent Data Corruption, and the second pipeline stage is more vulnerable to Silent Data Corruption than the first.

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Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%