2019
DOI: 10.1109/tmtt.2019.2909878
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Dynamic Dual-Gate Bias Modulation for Linearization of a High-Efficiency Multistage PA

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Cited by 16 publications
(10 citation statements)
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“…The device under test (DUT) is driven by the radio frequency (RF) signal and the time‐aligned gate and drain voltages. Time alignment for both gate and drain signals is performed using the method described in [16]. An equalisation function is applied to gate signals to compensate for the parasitics of the interconnect to the DUT.…”
Section: Measurement Methods and Gate Shaping Function Optimisationmentioning
confidence: 99%
See 3 more Smart Citations
“…The device under test (DUT) is driven by the radio frequency (RF) signal and the time‐aligned gate and drain voltages. Time alignment for both gate and drain signals is performed using the method described in [16]. An equalisation function is applied to gate signals to compensate for the parasitics of the interconnect to the DUT.…”
Section: Measurement Methods and Gate Shaping Function Optimisationmentioning
confidence: 99%
“…A level shift is introduced to bring the voltage down to that needed for the quiescent VnormalG. The instrumentation amplifier output is then connected to the fixtured MMIC PA through spring‐loaded pins [16].…”
Section: Measurement Methods and Gate Shaping Function Optimisationmentioning
confidence: 99%
See 2 more Smart Citations
“…The static bias connections are bonded directly to off-MMIC 100 pF singe-layer capacitors which are then bonded to the BB SMD capacitors for low-frequency bypassing. The RF and drain supply paths are aligned using methods described in [28]. The minimum pulse width of the DSM is limited to 8 ns by two chips on the MLD: the ADCMP601 logical comparator and the ISO721M digital isolator chip.…”
Section: Supply Modulation Test Benchmentioning
confidence: 99%