Dynamic dead-instruction detection and elimination

Abstract

We observe a non-negligible fraction--3 to 16% in our benchmarks--of dynamically dead instructions, dynamic instruction instances that generate unused results. The majority of these instructions arise from static instructions that also produce useful results. We find that compiler optimization (specifically instruction scheduling) creates a significant portion of these partially dead static instructions. We show that most of the dynamically instructions arise from a small set of static instructions that produce dead values most of the time.We leverage this locality by proposing a dead instruction predictor and presenting a scheme to avoid the execution of predicted-dead instructions. Our predictor achieves an accuracy of 93% while identifying over 91% of the dead instructions using less than 5 KB of state. We achieve such high accuracies by leveraging future control flow information (i.e., branch predictions) to distinguish between useless and useful instances of the same static instruction.We then present a mechanism to avoid the register allocation, instruction scheduling, and execution of predicted dead instructions. We measure reductions in resource utilization averaging over 5% and sometimes exceeding 10%, covering physical register management (allocation and freeing), register file read and write traffic, and data cache accesses. Performance improves by an average of 3.6% on an architecture exhibiting resource contention. Additionally, our scheme frees future compilers from the need to consider the costs of dead instructions, enabling more aggressive code motion and optimization. Simultaneously, it mitigates the need for good path profiling information in making inter-block code motion decisions.

Cross-layer early reliability evaluation: Challenges and promises

“…The work published in [31] analyzes various compiler optimization effects on the AVF of an embedded processor. Similar approaches at the compiler level have been also proposed in [32] and [33]. In [34] the authors proposed a first attempt of performing static analysis of a computer system including its software.…”

Cross-Layer Early Reliability Evaluation for the Computing cOntinuum

“…The work published in [30] analyzes various compiler optimization effects on the AVF of an embedded processor. Similar approaches at the compiler level have been also proposed in [31] and [32]. In [33] the authors proposed a first attempt of performing static analysis of a computer system including its software.…”

Continuous Optimization

“…We believe dead code should be removed in an off-the-critical-path dynamic optimizer, such as in [9], where latency is less critical. A speculative, in-pipeline technique for dead code removal [6] was shown to improve performance on a resource-bound machine. Including this technique, however, more than doubles our required chip real estate, but is a plausible addition for a resource-bound machine.…”

“…Although continuous optimization can be adapted for optimizing instruction traces, it is not limited to discrete regions, i.e., it can impact a greater span of instructions. There have been numerous in-pipeline optimization techniques [4,6,21,23,24,27]. Continuous optimization subsumes and extends many of them by aggressively optimizing dataflow through registers and memory to reduce dataflow height and to increase instruction-level parallelism (ILP).…”