Dynamic capping of rename registers for SMT processors

Sheikh, Marwa Naveed; Lin, Wei-Ming

doi:10.1016/j.sysarc.2019.101637

Cited by 2 publications

(4 citation statements)

References 22 publications

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“…Lin also proposed a dynamic physical register file capping scheme that allows thread-based individual capping in SMT processors [17].…”

Section: Heuristics For Smt Resource Managementmentioning

confidence: 99%

“…Second, the heuristics that we focus on may not always have the same mindset. For instance, all those in [4][5][6] focus on resource partitioning, whereas those of [14][15][16][17] focus on resource capping, which might be a quite different task compared to partitioning from time to time. In this study, we focus on two well-known heuristics (i.e.…”

Section: Motivationmentioning

confidence: 99%

“…Güngörer and Küçük utilized a hill-climbing algorithm to dynamically partition the physical register files among threads in an SMT processor [16]. Finally, Sheikh and Lin also proposed a dynamic physical register file capping scheme that allows thread-based individual capping in SMT processors [17].…”

Section: Heuristics For Smt Resource Managementmentioning

confidence: 99%

See 2 more Smart Citations

Hyperheuristics for explicit resource partitioning in simultaneous multithreadedprocessors

Güney¹,

Poyraz²,

Küçük³

et al. 2020

Turk J Elec Eng & Comp Sci

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In simultaneous multithreaded (SMT) processors, various data path resources are concurrently shared by many threads. A few heuristic approaches that explicitly distribute those resources among threads with the goal of improved overall performance have already been proposed. A selection hyperheuristic is a high-level search methodology that mixes a predetermined set of heuristics in an iterative framework to utilize their strengths for solving a given problem instance. In this study, we propose a set of selection hyperheuristics for selecting and executing the heuristic with the best performance at a given stage. To the best of our knowledge, this is one of the first studies implementing a hyperheuristic algorithm on hardware. The results of our experimental study show that hyperheuristics are indeed capable of improving the performance of the studied workloads. Our best performing hyperheuristic achieves better throughput than both baseline heuristics in 5 out of 12 workloads and gives about 15% peak performance gain. The average performance gains over the well-known hill-climbing and adaptive resource partitioning heuristics are about 5% and 2%, respectively.

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“…Lin also proposed a dynamic physical register file capping scheme that allows thread-based individual capping in SMT processors [17].…”

Section: Heuristics For Smt Resource Managementmentioning

confidence: 99%

Section: Motivationmentioning

confidence: 99%

See 1 more Smart Citation

Hyperheuristics for explicit resource partitioning in simultaneous multithreadedprocessors

Güney¹,

Poyraz²,

Küçük³

et al. 2020

Turk J Elec Eng & Comp Sci

View full text Add to dashboard Cite

show abstract

“…Although the dedicated structures do not impose much of a research challenge, shared structures require special research attention. There are plenty of studies in the literature that achieve to improve performance by analyzing shared structures such as caches [1,2], write buffer entries [3], and register files [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Dynamic issue queue capping for simultaneous multithreaded processors

Güney¹,

Kuru²,

Sari³

et al. 2021

Turk J Elec Eng & Comp Sci

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A simultaneous multithreaded (SMT) processor mixes multiple instruction streams in its superscalar out-oforder execution core for higher throughput. To achieve this, a superscalar processor is modified in such a way that some of its resources are duplicated and the rest is shared among multiple threads. The issue queue (IQ), which holds all waiting instructions until they become ready and scheduled for execution, is among these shared resources. A baseline unmanaged IQ can give an unexpectedly low performance since a hungry thread can tie up most of the IQ entries.This type of scenario is also worse in terms of the fairness metric since some of the threads may experience starvation.Earlier studies propose both static and a limited type of dynamic capping of the IQ entries for regulating IQ traffic and providing better SMT throughput and fairness. In this study, we propose an efficiency-based dynamic capping (EDC) algorithm that calculates an efficiency metric for each thread and allocates the IQ entries for maximizing the throughput and the fairness metrics. EDC gives 3.6% better throughput and 3.9% better fairness results compared to the current state-of-the-art algorithms, on the average.

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Dynamic capping of rename registers for SMT processors

Cited by 2 publications

References 22 publications

Hyperheuristics for explicit resource partitioning in simultaneous multithreadedprocessors

Hyperheuristics for explicit resource partitioning in simultaneous multithreadedprocessors

Dynamic issue queue capping for simultaneous multithreaded processors

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