Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

Anis, Mohab; Areibi, Shawki; Mahmoud, M. A.; Elmasry, M.I.

doi:10.1109/dac.2002.1012673

Cited by 85 publications

(49 citation statements)

References 6 publications

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“…In [25] and [12] a module-based structure and a corresponding sizing algorithm is presented. In the cluster-based structure [4], a module is decomposed into several clusters supported by corresponding sleep transistors. Recently, most industrial power-gating designs have adopted the Distributed Sleep Transistor Network (DSTN) [8,23,31] implementation, which uses the current discharge balance to further reduce the total sizes of sleep transistors.…”

Section: Existing Power-gating Techniquesmentioning

confidence: 99%

An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)

Chowdhury

Khaled

Gjanci

2010

Circuits Syst Signal Process

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Leakage has become one of the most dominant factors of power consumption and signal integrity of nanometer-scale integrated circuits. Recently, powergating structures have proven to be effective in controlling leakage. In this paper an alternative dual-V th reduced power-gating structure is proposed for better reduction of leakage currents, especially for low-power and high-performance portable devices. The proposed technique maintains an intermediate power-saving state as well as the conventional power cut-off state. The experimental results have demonstrated that the proposed technique can significantly reduce leakage current and associated power consumptions during the HOLD and CUT-OFF modes. In addition, an analysis of ground bounce due to power-mode transition in power-gating structures is presented. It is demonstrated that the proposed technique provides a way to control ground bounce during power-mode transition. Due to the presence of the intermediate state, its stepwise turning on feature will provide higher reduction of the magnitudes of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground as compared to other similar techniques.

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Section: Existing Power-gating Techniquesmentioning

confidence: 99%

An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)

Chowdhury

Khaled

Gjanci

2010

Circuits Syst Signal Process

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“…Gate clustering in [5] is proposed to cluster different low V th logical gates into sleep transistors in order that simultaneous currents flowing from logical gates to sleep transistors satisfy the tolerance of maximum currents of the given size of sleep transistor. In these clusters, each sleep transistor shares a common virtual network with the logical gates in the same cluster.…”

Section: Introductionmentioning

confidence: 99%

“…The existing methods focus at sizing and clustering the sleep transistors [5][6][7][8][9], without a close consideration of the virtual supply networks reduction, which can result in serious interconnect resistance and parasitic capacitance effects on circuit performance [9][10][11]. The large RC time constant on virtual supply networks will impact the performance in two ways.…”

Section: Introductionmentioning

confidence: 99%

“…In the previous works on MTCMOS, several strategies have been proposed on gate-level power consumption design [5][6][7][8][9]. Gate clustering in [5] is proposed to cluster different low V th logical gates into sleep transistors in order that simultaneous currents flowing from logical gates to sleep transistors satisfy the tolerance of maximum currents of the given size of sleep transistor.…”

Section: Introductionmentioning

confidence: 99%

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An MTCMOS technology for low-power physical design

et al. 2009

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“…The technique employs sleep transistors (ST) at the standby mode to isolate the power supply. As a result, the circuit speed at the active mode degrades due to extra resistance caused by the presence of sleep transistors (Anis et al 2002). Consequently, the sizing of sleep transistor is critical to the performance, the leakage power saving, and the noise immunity of MTCMOS circuits ).…”

mentioning

confidence: 99%

Modeling leakage power reduction in VLSI as optimization problems

2007

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Reducing power dissipation is one of the most important issues in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. Multi-Threshold CMOS (MTCMOS) technology has emerged as a promising technique to reduce leakage power. This paper first introduces how to model the sleep transistor sizing problem in the MTCMOS circuits as a Bin-Packing Problem (BPP). The gate-clustering BPP and the First-Fit (FF) techniques are also introduced to further improve the solution quality. To take the circuit's routing complexity into consideration which is critical for Deep Sub-Micron (technologies that are 0.25 µm and below) (DSM) implementations, a Set-Partitioning Problem (SPP) is then formed. However, this highly constrained model limits it's application for large circuit design. A Set-Covering (SCP) model is therefore investigated to efficiently solve the problem.

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Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

Cited by 85 publications

References 6 publications

An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)

An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)

An MTCMOS technology for low-power physical design

Modeling leakage power reduction in VLSI as optimization problems

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