DUNE-a multilayer gridless routing system

Cong, J.; Fang, Jie; Khoo, Kei-Yong

doi:10.1109/43.920694

Cited by 52 publications

(74 citation statements)

References 34 publications

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“…At the uncoarsening stage, we perform detailed routing. Further, the unroutable nets are handled by point-to-path maze routing [5], [9], [24] and rip-up and reroute to refine the routing solution level by level.…”

Section: )mentioning

confidence: 99%

“…Recently, Cong et al proposed a pioneering multilevel global-routing approach for large-scale, full-chip, routability-driven routing [8]. Cong et al later proposed an enhanced multilevel routing system named MARS [9], which incorporates resource reservation, a graph-based Steiner tree heuristic and a history-based multi-iteration scheme to improve the quality of the multilevel routing algorithm in [8]. The final results of both of the multilevel algorithms are tile-to-tile paths for all the nets.…”

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confidence: 99%

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Crosstalk- and performance-driven multilevel full-chip routing

Chang

Chen

et al. 2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we propose a novel framework for fast multilevel routing considering crosstalk and performance optimization. To handle the crosstalk minimization problem, we incorporate an intermediate stage of layer/track assignment into the multilevel routing framework. For performance-driven routing, we propose a novel minimum-radius minimum-cost spanning tree heuristic for global routing. Compared with the state-of-the-art multilevel routing with the routability mode, the experimental results show that our router achieved a 6.7X runtime speedup, reduced the respective maximum and average crosstalk (coupling length) by about 30% and 24%, reduced the respective maximum and average delay by about 15% and 5%. Compared with the timing-driven mode, the experimental results show that our router still achieved a 5.9X runtime speedup, reduced the respective maximum and average crosstalk by about 35% and 23%, reduced the respective maximum and average delay by about 7% and 10% in comparable routability, and resulted in fewer failed nets.

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Section: )mentioning

confidence: 99%

mentioning

confidence: 99%

Crosstalk- and performance-driven multilevel full-chip routing

Chang

Chen

et al. 2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…We introduced a number of efficient techniques in the multilevel routing scheme, including resource reservation, graph-based Steiner tree heuristic and history-based iterative refinement. We compared our multilevel framework with a recently published three-level routing flow [1]. Experimental results show that MARS helps to improve the completion rate by over 10%, and the runtime by 11 7 .…”

Section: Mars-a Multilevel Full-chipmentioning

confidence: 99%

“…In a recent work [1], a three-level routing scheme with an additional wire-planning phase between the performance-driven global routing and the detailed routing was proposed for deep submicron very large scale integration (VLSI) routing, as shown in Fig. 3.…”

Section: Introductionmentioning

confidence: 99%

MARS-a multilevel full-chip gridless routing system

Cong

Fang

Xie

et al. 2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper presents MARS, a novel multilevel full-chip gridless routing system. The multilevel framework with recursive coarsening and refinement allows for scaling of our gridless routing system to very large designs. The downward pass of recursive coarsening builds the representations of routing regions at different levels while the upward pass of iterative refinement allows a gradually improved solution. We introduced a number of efficient techniques in the multilevel routing scheme, including resource reservation, graph-based Steiner tree heuristic and history-based iterative refinement. We compared our multilevel framework with a recently published three-level routing flow [1]. Experimental results show that MARS helps to improve the completion rate by over 10%, and the runtime by 11 7 .Index Terms-Design automation, routing optimization methods, very large scale integration (VLSI).

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“…The gridless routing, however, is much more difficult than the grid-based routing because the solution space of gridless routing is significantly larger than that of grid-based routing. Cong et al in [6] proposed a three-level routing scheme with a wire-planning phase between the global routing and the detailed routing. However, for large-scale designs, even with the three-level routing system, the problem size at each level may still be very large.…”

Section: (A)mentioning

confidence: 99%

A novel framework for multilevel full-chip gridless routing

Chen

Chang

Lin³

Asia and South Pacific Conference on Design Automation, 2006.

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Abstract-Due to its great flexibility, gridless routing is desirable for nanometer circuit designs that use variable wire widths and spacings. Nevertheless, it is much more difficult than grid-based routing because of its larger solution space. In this paper, we present a novel "V-shaped" multilevel framework (called VMF) for full-chip gridless routing. Unlike the traditional "Λ-shaped" multilevel framework (inaccurately called the "Vcycle" framework in the literature), our VMF works in the V-shaped manner: top-down uncoarsening followed by bottom-up coarsening. Based on the novel framework, we develop a multilevel full-chip gridless router (called VMGR) for large-scale circuit designs. The top-down uncoarsening stage of VMGR starts from the coarsest regions and then processes down to finest ones level by level; at each level, it performs global pattern routing and detailed routing for local nets and then estimate the routing resource for the next level. Then, the bottom-up coarsening stage performs global maze routing and detailed routing to reroute failed connections and refine the solution level by level from the finest level to the coarsest one. We employ a dynamic congestion map to guide the global routing at all stages and propose a new cost function for congestion control. Experimental results show that VMGR achieves the best routability among all published gridless routers based on a set of commonly used MCNC benchmarks. Besides, VMGR can obtain significantly less wirelength, smaller critical path delay, and smaller average net delay than the previous works. In particular, VMF is general and thus can readily apply to other problems.

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DUNE-a multilayer gridless routing system

Cited by 52 publications

References 34 publications

Crosstalk- and performance-driven multilevel full-chip routing

Crosstalk- and performance-driven multilevel full-chip routing

MARS-a multilevel full-chip gridless routing system

A novel framework for multilevel full-chip gridless routing

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