Dual threshold voltage and sleep switch dual threshold voltage DOIND approach for leakage reduction in domino logic circuits

Shah, Ambika Prasad; Neema, Vaibhav; Daulatabad, Shreeniwas; Singh, Pooja

doi:10.1007/s00542-017-3437-2

Cited by 15 publications

(9 citation statements)

References 17 publications

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“…From Table 1, the proposed circuit required 25.03% less area than the conventional ST circuit. For high performance and low power, the PDP should be as small as possible, and at the same, less area overhead is preferable [9]. Here, the proposed FOM is expressed as

FOM = \frac{1}{PD {normalP}_{normalnorm} \times A_{normalnorm}},

where

PD {normalP}_{normalnorm}

and

A_{normalnorm}

are the normalised PDP and area, respectively.…”

Section: Resultsmentioning

confidence: 99%

NMOS only Schmitt trigger circuit for NBTI resilient CMOS circuits

et al. 2018

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A novel N-type MOS (NMOS) only Schmitt trigger with voltage booster (NST-VB) circuit is presented. The proposed NST-VB circuit uses NMOS transistors in both pull-up and pull-down networks to reduce the effect of negative bias temperature instability (NBTI) on the circuit. The proposed circuit is less affected by both inter-die and intra-die process variations in consequence of NMOS only structure. Owing to NBTI, the increase in delay for the proposed NST-VB circuit is only 0.47% as compared with 7.2% for conventional Schmitt trigger after the stress time of three years. For the viability of the proposed circuit figure of merit (FOM) is used as a performance metric and it is found that the proposed circuit has 15.35× and 3.53× improved FOM as compared with the conventional Schmitt trigger and NMOS inverter, respectively.

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FOM = \frac{1}{PD {normalP}_{normalnorm} \times A_{normalnorm}},

where

PD {normalP}_{normalnorm}

and

A_{normalnorm}

are the normalised PDP and area, respectively.…”

Section: Resultsmentioning

confidence: 99%

NMOS only Schmitt trigger circuit for NBTI resilient CMOS circuits

et al. 2018

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“…Cin indicates the input capacitance. Although the non-saturation mode equation is complicated, it can be predicted the adequate first-order gate delay from the equation (3). At this instant, derivation of delay for other approaches have been achieved one by one and compared with the basic CMOS approach.…”

Section: Comparative Analysis Of Delaymentioning

confidence: 99%

“…To minimize power dissipation, many researchers have proposed different ideas from the device level to the architectural level [1]. There are numerous methods discussed to reduce leakage power in CMOS based circuit designing [2][3][4][5][6][7][8][9][10]. Each approach delivers a novel way to reduce leakage power, but the shortcomings of each approach limit the claim of each approach to be the best.…”

Section: Introductionmentioning

confidence: 99%

Forced stack sleep transistor (FORTRAN): A new leakage current reduction approach in CMOS based circuit designing

Kassa¹,

Misra²,

Nagaria

2021

FACTA U EE

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Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4- bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.

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“…Equation (1) [5] gives the average power dissipation of a domino logic circuit. is the power consumed during output transitions as a result of a short circuit between Vdd (supply) and ground, P switching is the power consumed as a result of charging and discharging of circuit capacitances and P leakage is the power consumed as a result of sub-threshold and gate leakage current [5,6]. With continuous transistor scaling, gate oxide thickness and threshold voltage decrease, but leakage power increases drastically.…”

Section: Introductionmentioning

confidence: 99%

INDIDO: A novel low-power approach for domino logic circuits

Mushtaq,

Akram,

Prasad

et al. 2024

Phys. Scr.

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Power dissipation in Nanoelectronic circuits at advanced technology nodes is dominated by leakage power dissipation. This is due to an increase in short channel effects in the scaled transistors. The VLSI industry is seeking alternative options to enhance the performance of portable electronic systems by ensuring higher speed and reduced power dissipation. In the ultra-deep submicron (DSM) regime, a new device called the fin-shaped field effect transistor (FinFET) was developed to replace CMOS technology. FinFET, a multi-gate device, significantly reduces power dissipation compared to planer MOS (Metal Oxide Semiconductor ) transistor, but it doesn't entirely resolve the issue. To further reduce power dissipation in the ultra DSM regime, low power approaches are required. Domino logic, a widely-used dynamic logic, is commonly utilized in high-speed VLSI architectures. In this research work, a novel INput Dependent Inverter DOmino (INDIDO) logic approach for low-power domino logic circuits using FinFET devices is proposed. A comparative analysis between the proposed INDIDO method and the existing approaches is performed for domino logic circuits for various performance metrics at the 16 nm technology node. In this research, various circuits like domino buffer, domino OR, domino AND, domino XOR and domino half adder are designed using the proposed INDIDO approach. The proposed INDIDO FinFET buffer circuit offers significant improvement in energy efficiency and FOM (Figure of Merit) by 53.18 % and 82% respectively as compared to conventional FinFET footed domino buffer circuit. Beside this, proposed circuits like INDIDO OR, INDIDO AND, INDIDO XOR and INDIDO Half adder circuit follow the same trend as INDIDO buffer circuit and show better performance parameters in comparison to the existing low power domino approaches as well. In addition to this, the proposed INDIDO buffer circuits are also analyzed for PVT(process voltage and temperature) variability. This whole analysis makes us to conclude that proposed INDIDO approach reduces power dissipation and delay penalty, have high noise tolerance capacity, more immunity against PVT variations and high energy efficiency in comparison to the already existing techniques.

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Dual threshold voltage and sleep switch dual threshold voltage DOIND approach for leakage reduction in domino logic circuits

Cited by 15 publications

References 17 publications

NMOS only Schmitt trigger circuit for NBTI resilient CMOS circuits

NMOS only Schmitt trigger circuit for NBTI resilient CMOS circuits

Forced stack sleep transistor (FORTRAN): A new leakage current reduction approach in CMOS based circuit designing

INDIDO: A novel low-power approach for domino logic circuits

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