Extended Abstracts of International Workshop on Gate Insulator. IWGI 2001 (IEEE Cat. No.01EX537)
DOI: 10.1109/iwgi.2001.967552
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Dual-poly CVD HfO/sub 2/ gate stack for sub-100 nm CMOS technology

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“…Recently, nano-technology has driven intense research on high k gate dielectric layers in nanoscale on Si as well as on compound semiconductor surfaces due to their importance in fundamental science and technological applications [1][2][3][4][5]. According to the latest International Technology Roadmap for Si, the rapid shrinkage of transistor [9][10].…”
Section: Introductionmentioning
confidence: 99%
“…Recently, nano-technology has driven intense research on high k gate dielectric layers in nanoscale on Si as well as on compound semiconductor surfaces due to their importance in fundamental science and technological applications [1][2][3][4][5]. According to the latest International Technology Roadmap for Si, the rapid shrinkage of transistor [9][10].…”
Section: Introductionmentioning
confidence: 99%