Dual Mode Logic Address Decoder

Yavits, Leonid; Taco, Ramiro; Shavit, Netanel; Stanger, Inbal; Fish, Alexander

doi:10.1109/iscas45731.2020.9180587

Cited by 6 publications

(8 citation statements)

References 13 publications

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“…DML allows a digital circuit to operate in dynamic or static mode [33], according to the system requirements. This is achieved by adding at least one additional clocked transistor to the static CMOS core [24,28], thus obtaining 4 different types of DML gates, as shown in Figure 1. Adding a pMOS transistor to the pull-up network (PUN) defines a Type-A DML gate, while adding a nMOS to the pull-down network (PDN) gives rise to a Type-B DML gate.…”

Section: Dual Mode Logic Overviewmentioning

confidence: 99%

“…If a DML gate has to be switched to the static mode, the CLK signal must be maintained at a high/low level for Type-A/Type-B gates. This turns off the clocked transistors resulting in a CMOS-like structure [28] with a minimal parasitic capacitance added to the output of each single gate [20].…”

Section: Dual Mode Logic Overviewmentioning

confidence: 99%

“…It is worth noting that the DML operation modes can be tuned at low level of design granularity according to the system requirements, designer considerations, or automatically by an input-driven control (as in this work) [22,25,[27][28][29]35]. This means that DML static and dynamic operations can be enabled at the same time in different portions of the circuit.…”

Section: Dual Mode Logic Overviewmentioning

confidence: 99%

“…Note that the AD can be seen as a NOR-NAND chain, thus making it particularly suitable for an efficient alternating Type-A/Type-B DML implementation. It is worth mentioning that Type-B headed gates are used on the first stage on the DML AD to correctly interface with standard CMOS logic [28].…”

Section: Address Decoder Architecturementioning

confidence: 99%

“…Even though previous work has already presented a DML Address Decoder (AD) [28], the novelty of this work revolves around the implementation of a controller to enable mixed mode operation [25,29] as well as the use of a non-conventional AD architecture based on [30]. An AD benchmark circuit was chosen since it is frequently used in register files, SRAM, DRAM, and other types of memories, therefore it's delay is a significant component of a memory global latency [28,31,32]. For comparison purposes, different ADs were also designed based on static CMOS, DML, and dynamic domino structures.…”

Section: Introductionmentioning

confidence: 99%

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Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder

et al. 2021

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This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism that mixes both of these modes of operation to simultaneously benefit from their inherent advantages. When performance is the primary target, the mixed operating mode is enabled, and the self-adjustment mechanism identifies at run time the logic gates that have to work in the energy-efficient mode (i.e., static mode), while those belonging to the critical path operate in the faster dynamic mode. Moreover, our address decoder can run in the fully static mode for the lowest energy consumption when speed is not a primary concern. A 65 nm CMOS technology was exploited to simulate and compare our solution with other logically equivalent dynamic and static designs. Operated in the mixed mode, the proposed circuit exhibits negligible speed reduction (8.7%) in comparison with a dynamic logic based design while presenting significantly reduced energy consumption (28%). On the contrary, further energy is saved (29%) with respect to conventional logic styles when our design runs in its energy efficient mode.

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Section: Dual Mode Logic Overviewmentioning

confidence: 99%

Section: Dual Mode Logic Overviewmentioning

confidence: 99%

Section: Dual Mode Logic Overviewmentioning

confidence: 99%

Section: Address Decoder Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder

et al. 2021

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High-performance and low-power decoder circuits for SRAMs using mixed-logic scheme

Xia,

Zhang,

Tian

et al. 2024

Integration

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High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

Escobar

Prócel

Trojman³

et al. 2021

2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS)

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This paper presents an energy-efficient singleclock-cycle binary Dual-Mode Logic (DML)-based comparator optimized to operate in the dynamic mode. The parallel-prefix architecture is implemented to ensure high speed, whereas low power consumption is guaranteed by reducing the switching activities of internal nodes. Domino Logic (DL) and DML implementations are compared in terms of delay and energy for different supply voltages in the 32 nm technology. We demonstrate an average improvement of 5% in both energy and delay when the DML design is operating in the dynamic mode compared to its conventional domino counterpart. Moreover, the DML design operating in the static mode allows to save up to 43% energy consumption compared to the equivalent domino logic-based implementation.

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Dual Mode Logic Address Decoder

Cited by 6 publications

References 13 publications

Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder

Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder

High-performance and low-power decoder circuits for SRAMs using mixed-logic scheme

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

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