Dual-Mode CMOS Power Amplifier Based on Load-Impedance Modulation

Lim, Wonseob; Kang, Hyunuk; Lee, Wooseok; Bae, Ji Cheol; Oh, Sang-Jin; Oh, Hansik; Chae, Seunghwan; Hwang, Keum Cheol; Yang, Youngoo

doi:10.1109/lmwc.2018.2871339

Cited by 11 publications

(3 citation statements)

References 6 publications

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“…The proposed PA provides high linear output power with high efficiency, while supporting an external PA mode for NB-IoT applications. When it is tested with a NB-IoT signal, compared with the results of [20], the output power is higher than 7 dB, and the PAE in this work is much higher than that reported elsewhere [20], while meeting −45 dBc ACLR. In addition, the proposed PA provides the highest saturated output power and PAE compared to other works supporting an external PA mode.…”

Section: Fabrication and Measurement Resultsmentioning

confidence: 47%

A Dual-Mode CMOS Power Amplifier with an External Power Amplifier Driver Using 40 nm CMOS for Narrowband Internet-of-Things Applications

Ahn,

Oh,

Choi

et al. 2024

Nanomaterials

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The narrowband Internet-of-Things (NB-IoT) has been developed to provide low-power, wide-area IoT applications. The efficiency of a power amplifier (PA) in a transmitter is crucial for a longer battery lifetime, satisfying the requirements for output power and linearity. In addition, the design of an internal complementary metal-oxide semiconductor (CMOS) PA is typically required when considering commercial applications to include the operation of an optional external PA. This paper presents a dual-mode CMOS PA with an external PA driver for NB-IoT applications. The proposed PA supports an external PA mode without degrading the performances of output power, linearity, and stability. In the operation of an external PA mode, the PA provides a sufficient gain to drive an external PA. A parallel-combined transistor method is adopted for a dual-mode operation and a third-order intermodulation distortion (IMD3) cancellation. The proposed CMOS PA with an external PA driver was implemented using 40 nm-CMOS technology. The PA achieves a gain of 20.4 dB, a saturated output power of 28.8 dBm, and a power-added efficiency (PAE) of 57.8% in high-power (HP) mode at 920 MHz. With an NB-IoT signal (200 kHz π/4-differential quadrature phase shift keying (DQPSK)), the proposed PA achieves 24.2 dBm output power (Pout) with a 31.0% PAE, while satisfying −45 dBc adjacent channel leakage ratio (ACLR). More than 80% of the current consumption at 12 dBm Pout could be saved compared to that in HP mode when the proposed PA operates in low-power (LP) mode. The implemented dual-mode CMOS PA provides high linear output power with high efficiency, while supporting an external PA mode. The proposed PA is a good candidate for NB-IoT applications.

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Section: Fabrication and Measurement Resultsmentioning

confidence: 47%

A Dual-Mode CMOS Power Amplifier with an External Power Amplifier Driver Using 40 nm CMOS for Narrowband Internet-of-Things Applications

Ahn,

Oh,

Choi

et al. 2024

Nanomaterials

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“…As a result, enhanced back-off efficiency range and broad bandwidth gradually become crucial targets for contemporary PAs. In addition to established technologies like Envelope Tracking (ET) [1] and Doherty Power Amplifiers [2]- [4], recent advancements have introduced innovative architectures and techniques [5], [6], such as load-modulated balanced amplifiers [7]- [17]. These new developments offer remarkable improvements in efficiency, Output Back-Off (OBO) range, and bandwidth capabilities, representing significant strides in amplifier technology.…”

Section: Introductionmentioning

confidence: 99%

Linear Hybrid Asymmetrical Load-Modulated Balanced Amplifier With Multiband Reconfigurability and Antenna-VSWR Resilience

Guo,

Cao,

Chen

2024

IEEE Trans. Microwave Theory Techn.

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This paper presents the first-ever highly linear and load-insensitive three-way load-modulation power amplifier (PA) based on reconfigurable hybrid asymmetrical load modulated balanced amplifier (H-ALMBA). Through proper amplitude and phase controls, the carrier, control amplifier (CA), and two peaking balanced amplifiers (BA1 and BA2) can form a linear high-order load modulation over wide bandwidth. Moreover, it is theoretically unveiled that the load modulation behavior of H-ALMBA can be insensitive to load mismatch by leveraging bias reconfiguration and the intrinsic load-insensitivity of balanced topology. Specifically, the PA's linearity and efficiency profiles can be maintained against arbitrary load mismatch through ZLdependent reconfiguration of CA supply voltage (VDD,CA) and turning-on sequence of BA1 and BA2. Based on the proposed theory, an RF-input linear H-ALMBA is developed with GaN transistors and wideband quadrature hybrids. Over the design bandwidth from 1.7-2.9 GHz, an efficiency of 56.8%−72.9% at peak power and 49.8%−61.2% at 10-dB PBO are measured together with linear AMAM and AMPM responses. In modulated evaluation with 4G LTE signal, an EVM of 3.1%, ACPR of −39 dB, and average efficiency of up to 52% are measured. Moreover, the reconfigurable H-ALMBA experimentally maintains an excellent average efficiency and linearity against arbitrary load mismatch at 2 : 1 VSWR, and this mismatch-resilient operation can be achieved at any in-band frequencies. The overall measured performance favorably outperforms the state-of-the-art.

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“…As the data rates of rapid wireless communication systems have increased significantly, the linearity of power amplifiers has gained significant importance [1][2][3][4]. Accordingly, many parameters define the linearity of power amplifiers, such as the third-order intermodulation distortion (IMD3), amplitude-toamplitude (AM-AM) distortion, amplitude-to-phase (AM-PM) distortion, and so on.…”

Section: Introductionmentioning

confidence: 99%

Suppression of Imd3 in Cmos Power Amplifier Using Bias Circuit of Common-Gate Transistor With Cascode Structure

Kim¹,

Lee²,

Yoo³

et al. 2019

PIER M

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In this study, we propose a technique to improve the linearity of complementary metaloxide semiconductor (CMOS) power amplifiers with a cascode structure. From the investigation of the influence of the impedance of an envelope signal on the linearity, we find that the load impedance of the envelope signal of the common-source transistor should be reduced. To obtain alow load impedance of the envelope signal, we reduce the value of the gate resistor of the common-gate transistor. After investigating the influences of the value of the resistance on the third-order intermodulation distortion (IMD3), we extract the optimum value of the resistance. We also consider the electrostatic discharge protection issue and the effects of the variations in the parasitic components of bond-wires, in the process of the extraction of the optimum value. To verify the feasibility of the optimization technique of the resistance of the bias circuit of the common-gate transistor of the amplifier, we design a power amplifier using a 180-nm RFCMOS process for wireless local area network (WLAN) 802.11n applications. We obtain the measured maximum linear output power of 22.2 dBm with a 26.7% power-added efficiency and a 3.72% error vector magnitude. We use an 802.11n modulated signal with 64-QAM (MCS7) at 65 Mb/s. From the measured results, we successfully verify the feasibility of the proposed optimization technique of the resistance of the bias circuit of the common-gate transistor.

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Dual-Mode CMOS Power Amplifier Based on Load-Impedance Modulation

Cited by 11 publications

References 6 publications

A Dual-Mode CMOS Power Amplifier with an External Power Amplifier Driver Using 40 nm CMOS for Narrowband Internet-of-Things Applications

A Dual-Mode CMOS Power Amplifier with an External Power Amplifier Driver Using 40 nm CMOS for Narrowband Internet-of-Things Applications

Linear Hybrid Asymmetrical Load-Modulated Balanced Amplifier With Multiband Reconfigurability and Antenna-VSWR Resilience

Suppression of Imd3 in Cmos Power Amplifier Using Bias Circuit of Common-Gate Transistor With Cascode Structure

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