Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

Yeo, Yee-Chia; Lü, Qiang; Ranade, P.; Takeuchi, Hideki; Yang, K.J.; Polishchuk, I.; King, Tsu‐Jae; Hu, Chenming; Song, Seok-Zun; Luan, H.F.; Kwong, Dim‐Lee

doi:10.1109/55.919237

Cited by 95 publications

(17 citation statements)

References 6 publications

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“…The proposed device can be fabricated using various techniques. In literature, some techniques have been suggested to fabricate DGTFETs and DM-DGTFETs [15], [21]- [27] and some techniques have been employed to fabricate the DMG structures [28]- [30]. Due to the structural similarity, the proposed devices can also be fabricated by adapting these techniques.…”

Section: A Device Fabricationmentioning

confidence: 99%

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Garg

Saurabh

2020

IEEE J. Electron Devices Soc.

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Recently, a few compact logic function realizations such as AND, OR, NAND and NOR have been proposed using double-gate tunnel field-effect transistor (DGTFET) with independent gate-control. In this paper, using two-dimensional device simulations, we propose to realize the exclusive-OR (XOR) and exclusive-NOR (XNOR) logic functions. To implement an XOR function, a dual-material DGTFET (DM-DGTFET) is used. The structure is designed such that the band-to-band tunneling (BTBT) occurs at the boundary of these dual-material gates, rather than at the source-channel junction. Further, to realize the XNOR function, the gate-source and the gate-drain overlaps are used. The proposed DGTFET-based logic function implementations are able to modulate the current flow as per the required functionality, achieving an ON-state current by OFFstate current (ION /IOF F) ratio of order ∼ 10 9. Furthermore, it is demonstrated that a CMOS-type XNOR gate can be realized by combining the proposed XNOR and XOR functions in the pull-up and pull-down network, respectively.

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Section: A Device Fabricationmentioning

confidence: 99%

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Garg

Saurabh

2020

IEEE J. Electron Devices Soc.

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“…Subsequently, one of the metals is selectively removed from unwanted regions [23]. Additionally, metal wet etching and other advanced fabrication processes can be used for fabricating DMG, as demonstrated in [24]- [26]. In this paper, all simulations have been carried out using the ATLAS version 5.22.1.R [27].…”

Section: Device Structure and Simulation Setupmentioning

confidence: 99%

Exploiting Within-Channel Tunneling in a Nanoscale Tunnel Field-Effect Transistor

Garg

Saurabh

2020

IEEE Open J. Nanotechnol.

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In this paper, using device simulations, we investigate electrical characteristics of a tunnel field-effect transistor (TFET) in which band-to-band tunneling (BTBT) occurs dominantly within the channel, rather than at source-channel junction. The within-channel BTBT is enabled by sharp bandbending induced by the dual material gate (DMG). The workfunctions of two metal gates are chosen, such that the surface potential profile exhibits a distinct step at the DMG interface. Consequently, even under equilibrium condition, a high lateral electric field and an abrupt tunneling junction exist at the DMG interface. When a small gate voltage is applied, the inherent lateral electric field aids in creating an abrupt band alignment and obtaining a small tunneling width. As a result, an excellent average subthreshold swing is obtained in the proposed device. We have also investigated scaling of channel lengths in the proposed device and have demonstrated that within-channel tunneling can be exploited for channel lengths of 40nm and above. Furthermore, low drain threshold voltage and suppressed drain-induced barrier lowering can be obtained in the proposed device. Moreover, in contrast to conventional TFETs, electrical characteristics of the proposed device are less susceptible to source doping variations and shift in gate-edge with respect to the source-channel junction. Index Terms-Tunnel field-effect transistor, dual material gate, subthreshold swing, threshold voltage, lateral electric field, process-induced variations.

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“…The first demonstration of a dual-metal gate CMOS using Ti as n-metal gate and Mo as p-metal gate, respectively, together with SiO x N y as dielectric, was reported in 2002. The device showed negligible gate depletion, remarkably reduced gate leakage and acceptable channel mobility [133]. The TiN/Ti double layer was deposited by sputtering, targeting at a theoretical work function of metal Ti on SiO x N y of 4.36 eV.…”

Section: Ald Of N-type Metal Gatementioning

confidence: 99%

Atomic Layer Deposition (ALD) of Metal Gates for CMOS

Zhao

Xiang

2019

Applied Sciences

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The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.

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Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

Cited by 95 publications

References 6 publications

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Exploiting Within-Channel Tunneling in a Nanoscale Tunnel Field-Effect Transistor

Atomic Layer Deposition (ALD) of Metal Gates for CMOS

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