Dual Gate ZnO-Based Thin-Film Transistors Operating at 5 V: nor Gate Application

Park, C.H.; Lee, K.H.; Oh, Min Suk; Lee, K.; Im, Seongil; Lee, B.H.; Sung, Myung Mo

doi:10.1109/led.2008.2007973

Cited by 27 publications

(9 citation statements)

References 10 publications

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“…We note that most papers report as a common feature an increased on/off current ratio,18, 20, 21, 25–28 improved mobility,18, 28 and a steeper subthreshold slope 18, 20, 26, 28. Chua et al report that dual‐gate transistors can achieve a considerably deeper gate modulation than possible with single gating.…”

Section: Discrete Dual‐gate Transistormentioning

confidence: 83%

“…In analog circuits, advantages of DGTFTs have been found in the increase of the transconductance leading to an increased gain band width of differential amplifiers 6. Furthermore, DGTFTs have been implemented to operate as self‐contained logic gates 20, 21, 27. Finally, DGTFTs in a ‐Si:H technologies targeting AM‐LCD and AMOLED displays are discussed.…”

Section: Dual‐gate Logic Gates and Integrated Circuitsmentioning

confidence: 99%

“…Various papers based on a range of other organic semiconductors were published in the following years. In 2009, ZnO and “InGaZnO” DGTFTs were demonstrated by various groups from Korea 19–21. Finally, in 2010 the group of Avouris presented graphene based DGTFTs 22, 23.…”

Section: Introductionmentioning

confidence: 99%

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Dual‐Gate Thin‐Film Transistors, Integrated Circuits and Sensors

et al. 2011

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The first dual‐gate thin‐film transistor (DGTFT) was reported in 1981 with CdSe as the semiconductor. Other TFT technologies such as a‐Si:H and organic semiconductors have led to additional ways of making DGTFTs. DGTFTs contain a second gate dielectric with a second gate positioned opposite of the first gate. The main advantage is that the threshold voltage can be set as a function of the applied second gate bias. The shift depends on the ratio of the capacitances of the two gate dielectrics. Here we review the fast growing field of DGTFTs. We summarize the reported operational mechanisms, and the application in logic gates and integrated circuits. The second emerging application of DGTFTs is sensitivity enhancement of existing ion‐sensitive field‐effect transistors (ISFET). The reported sensing mechanism is discussed and an outlook is presented.

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Section: Discrete Dual‐gate Transistormentioning

confidence: 83%

Section: Dual‐gate Logic Gates and Integrated Circuitsmentioning

confidence: 99%

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Dual‐Gate Thin‐Film Transistors, Integrated Circuits and Sensors

et al. 2011

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“…ZnO [2] and gallium indium zinc oxide (GIZO) [3] with their higher mobilities were shown to be suitable for AM-LCD and AM-OLED displays, respectively. Even higher mobilities were shown to be feasible using ZnO [4], [5], GIZO [6], InGaO 3 [7], and zinc tin oxide [8] thin films, which led to the demonstration of TFT-based high speed and logic circuits [9]- [12]. Recently, the microwave amplification potential of metal-oxide TFTs was explored using smaller gate length devices.…”

Section: Introductionmentioning

confidence: 99%

High-Frequency ZnO Thin-Film Transistors on Si Substrates

Bayraktaroglu

Leedy

Neidhard

2009

IEEE Electron Device Lett.

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Record microwave frequency performance was achieved with nanocrystalline ZnO thin-film transistors fabricated on Si substrates. Devices with 1.2-μm gate lengths and Au-based gate metals had current and power gain cutoff frequencies of f T = 2.45 GHz and f max = 7.45 GHz, respectively. Same devices had drain-current on/off ratios of 5 × 10 10 , exhibited no hysteresis effects and could be operated at a current density of 348 mA/mm. The microwave performances of devices with 1.2-and 2.1-μm gate lengths and 50-and 100-μm gate widths were compared.Index Terms-FET, high frequency, microwave, nanocrystalline, on/off ratio, pulsed laser deposition, thin-film transistors (TFTs), ZnO.

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“…Doublegate TFTs are of interest because they allow threshold voltage tuning, improved device performance, and circuit applications like mixers. [2,3] We have previously reported bottom-gate ZnO TFTs and circuits fabricated on glass and flexible polymeric substrates using plasma enhanced atomic layer deposition (PEALD) [4,5]. Here we report double-gate ZnO TFTs and circuits fabricated on glass substrates using PEALD with a maximum process temperature of 200 ˚C.…”

mentioning

confidence: 98%

Low-voltage ZnO double-gate thin film transistor circuits

Ramirez

Sun

et al. 2012

70th Device Research Conference

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We report here double-gate ZnO thin film transistor (TFT) circuits with operation at low voltage. TFTs with low voltage operation have been reported previously, but often use very thin (few nm thick) gate dielectric which may limit manufacturability [1]. Oxide semiconductor-based TFTs have been extensively studied as competitive candidates for next-generation display technology and other large-area electronics. For many applications, operation at voltages compatible with low-voltage CMOS is important. Doublegate TFTs are of interest because they allow threshold voltage tuning, improved device performance, and circuit applications like mixers. [2,3] We have previously reported bottom-gate ZnO TFTs and circuits fabricated on glass and flexible polymeric substrates using plasma enhanced atomic layer deposition (PEALD) [4,5]. Here we report double-gate ZnO TFTs and circuits fabricated on glass substrates using PEALD with a maximum process temperature of 200 ˚C. Compared to bottom-gate ZnO TFTs, doublegate ZnO TFTs have higher mobility, and reduced substhreshold slope. In these devices, the top gate can be used to vary the bottom-gate threshold voltage by more than 4 V. This allows the logic transition point for circuits to be adjusted as desired and allows logic operation at low voltage. 15 stage double-gate ZnO TFT ring oscillators operate well with V DD = 1.2 V, I D = 32 µA, and propagation delay of 2.1 µs/stage. Figure 1 shows a schematic cross-section of a double-gate ZnO TFT. To fabricate the devices, a 100 nm Cr layer was deposited on borosilicate glass by sputtering and patterned by wet etching to form the bottom gates. Next, 32 nm thick Al 2 O 3 and 10 nm thick ZnO layers were deposited by PEALD and patterned by wet etching. Next, Ti source and drain contacts were deposited by sputtering and patterned by lift-off. An O 2 plasma step was used prior to Ti deposition to reduce contact resistance. Al 2 O 3 (32 nm thick) deposited by ALD at 200 °C was used for the top-gate dielectric and patterned by wet etching. 100 nm thick Cr was deposited by sputtering and patterned by wet etching to form the top gates. Linear region I D versus V GS and I D versus V DS characteristics are shown in figure 1 for a TFT with L = 20 µm, W = 200 µm, t oxbottom = t oxtop = 32 nm. Both bottom-gate with V topgate = 0 and top and bottom gates connected together device characteristics are shown in the figure. Bottom-gate operated TFTs have linear region mobility of 27 cm 2 /V⋅s; with top and bottom gates connected together the linear region mobility increases to 33 cm 2 /V⋅s. Figure 2 shows threshold voltage tuning of more than 4 V for bottom-gate TFT characteristics by varying the top-gate voltage from -3 V to 3V.The schematic diagram and micrograph of a double-gate TFT inverter with L drive = 5 µm, W drive = 50 µm, L load = 5 µm, W load = 10 µm (β ratio = 5) is shown in Figure 3. Top and bottom gates are connected together and to the source for the load TFT. The top gate of the drive TFT is varied to tune the bottom-gate TFT threshold ...

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Dual Gate ZnO-Based Thin-Film Transistors Operating at 5 V: nor Gate Application

Cited by 27 publications

References 10 publications

Dual‐Gate Thin‐Film Transistors, Integrated Circuits and Sensors

Dual‐Gate Thin‐Film Transistors, Integrated Circuits and Sensors

High-Frequency ZnO Thin-Film Transistors on Si Substrates

Low-voltage ZnO double-gate thin film transistor circuits

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