DSS: a distributed high-level synthesis system

Roy, J.; Kumar, Naveen; Dutta, Raj Gautam; Vemuri, Ranga

doi:10.1109/54.143143

Cited by 54 publications

(16 citation statements)

References 12 publications

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“…In addition, the exploration model attempts to minimize design latency by exploiting the task-level and operation-level parallelism. Nevertheless, the model can be changed to allow sharing by simply modifying the RTL estimation mechanism and introducing a suitable controller model [32].…”

Section: Definitions For Partitioned Task Graphmentioning

confidence: 99%

“…The USM representation can be used for: 1) high-level VLSI synthesis [32] where the goal is to synthesize a CMOS ASIC; 2) hardware-software co-synthesis [62] where the target architecture contains a general-purpose processor to implement software tasks and a coprocessor to implement the hardware tasks; and 3) adaptive system synthesis [26] where the target architecture is a dynamically reconfigurable multi-FPGA board with both local memories for each FPGA and a shared memory, and a crossbar type communication fabric.…”

Section: Introductionmentioning

confidence: 99%

“…These include data-flow graphs (DFG), mixed control-data flow graphs (CDFG), timed decision tables (TDT), and various flavors of graph-based and table-based formalisms sometimes augmented with global flow information such as module call graphs (MCG). Although many of these representations share common features, they also have application-specific features that inhibit their use across various types of synthesis systems.This section presents an overview of the Unified Specification Model, and provides insight on compatibility with VHDL.The USM representation can be used for: 1) high-level VLSI synthesis [32] where the goal is to synthesize a CMOS ASIC; 2) hardware-software co-synthesis [62] where the target architecture contains a general-purpose processor to implement software tasks and a coprocessor to implement the hardware tasks; and 3) adaptive system synthesis [26] where the target architecture is a dynamically reconfigurable multi-FPGA board with both local memories for each FPGA and a shared memory, and a crossbar type communication fabric.In the next sections, we present a detailed description of the Unified Specification Model and its semantics. …”

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confidence: 99%

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Computer Aided Engineering for Reconfigurable Computing (CAERC)

Vemuri¹

2001

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The public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Department of Defense, Washington Headquarters Services, Directorate for Information Operations and Reports (0704-0188), 1215 Jefferson Davis Highway, Suite 1204, Arlington, VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to any penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number. PLEASE DO NOT RETURN YOUR FORM TO THE ABOVE ADDRESS. REPORT DATE (DD-MM-YY)October 2001 2. REPORT TYPE Approved for public release; distribution unlimited. SUPPLEMENTARY NOTES ABSTRACT (Maximum 200 Words)Synthesis and Partitioning for Adaptive and Reconfigurable Computing Systems (SPARCS) is a computer aided engineering environment for reconfigurable computers. SPARCS contains software implementations of a variety of methods and algorithms for various subproblems for automating the task of producing designs for multi-FPGA (Field Programmable Gate Array) based reconfigurable computers. The SPARCS system includes tools for temporal partitioning, spatial partitioning, high-level synthesis, physical design, and arbiter synthesis. This is a comprehensive report on the SPARCS project, describing various techniques developed for solving these problems. In addition, this report contains some experimental results demonstrating the effectiveness of the SPARCS tools. Reconfigurable processors consisting of a sea of uncommitted FPGAs offer the same performance advantages of custom computing while retaining the flexibility of general purpose instruction architectures. In 1996, at the begining of this project, it was predicted that in near future reconfigurable processors can offer lOOx performance improvement over contemporary microprocessors, and 10-100x reduction in power/gate, 20x progress in density, and l,000,000x reduction in reconfiguration time compared to current reconfigurable devices.Unfortunately, state-of-the-art design synthesis methodologies were able to use perhaps 50-75% of the available gates at 30-50% of the maximum clocking rate of single reprogrammable device and were woefully inadequate in synthesizing multi-device systems. In order to deliver the performance expectations of reconfigurable architectures, dramatic improvements in the synthesis tools were necessary in both directions: (1) ability to synthesize to multiple device architectures, and, (2) improvement in utilization and delivered performance of each device. The goal of this project was to develop a coherent design synthesis and partitioning environment for co...

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Section: Definitions For Partitioned Task Graphmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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Computer Aided Engineering for Reconfigurable Computing (CAERC)

Vemuri¹

2001

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“…We report results for five RTL designs [14] (See Table 1): (1) Compress -a look-up table based compression algorithm; (2) Find -a sort-and-search chip; (3) FIFO -a First In First Out Queue; (4) Elliptic Wave Filter -a fifth-order filter; (5) Shuffle Exchange Network -implementation of "forward pass" functionality of a high speed reconfigurable shuffleexchange network [6].…”

Section: Resultsmentioning

confidence: 99%

Net clustering based macrocell placement

Alupoaei¹,

Katkoori²

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conferen

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“…In some related work, some researchers [14] have proposed a parallel system for distributed high level synthesis which uses coarse-grained parallelism to explore and evaluate many alternative VLSI designs efficiently. They propose a distributed version of force directed list scheduling in which each processor executes the FDLS algorithm on a separate module set.…”

Section: Introductionmentioning

confidence: 99%

Parallel algorithms for force directed scheduling of flattened and hierarchical signal flow graphs

Prabhakaran

Banerjee

Proceedings International Conference on Computer Design. VLSI in Computers and Processors

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DSS: a distributed high-level synthesis system

Cited by 54 publications

References 12 publications

Computer Aided Engineering for Reconfigurable Computing (CAERC)

Computer Aided Engineering for Reconfigurable Computing (CAERC)

Net clustering based macrocell placement

Parallel algorithms for force directed scheduling of flattened and hierarchical signal flow graphs

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