dsReliM: Power-constrained reliability management in Dark-Silicon many-core chips under process variations

Salehi, M T Zahraei; Shafique, Muhammad; Kriebel, Florian; Rehman, Semeen; Tavana, Mohammad Khavari; Ejlali, Alireza; Henkel, Jörg

doi:10.1109/codesisss.2015.7331370

Cited by 20 publications

(17 citation statements)

References 24 publications

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“…Dynamic Application Version Selection 1) Aging-aware [35,18] 2) DVFS [38,39] Core and Application Version Selection 1) Variation-aware [21] 2) Aging-aware [10] 3) Perf.-aware [21] 4) Dark Silicon [38] Program Reliability Estimation [37] Reliability and Resilience Modeling Application Resilience Modeling [41] Full-Processor Aging Modeling and Estimation [35] Fault Models (Transient, Permanent, # bitflips, SEUs, SETs)…”

Section: Run-time Systemmentioning

confidence: 99%

“…This technique demonstrates up to 60% power reductions while improving the reliability significantly. Similarly, in addition to redundancy, multiple voltage-frequency levels are introduced while considering the effects of dark silicon in multi/many-core heterogeneous processor [39]. This technique also considers the effects of soft errors and process variations in their reliability management system that provides up to 19% improved reliability under different design constraints [35].…”

Section: Variability-aware Reliability-heterogeneous Processor [21]: mentioning

confidence: 99%

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Fault-Tolerant Computing with Heterogeneous Hardening Modes

Kriebel

Khalid

Prabakaran

et al. 2020

Dependable Embedded Systems

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Fault-tolerance using (full-scale) redundancy-based techniques has been employed to detect and correct reliability errors (i.e., soft errors), but they pose significant area and power overhead. On the other hand, due to the masking and the error tolerance properties at different system layers and of different applications, respectively, reliable heterogeneous architectures have been emerged as an attractive design choice for power-efficient dependable computing platforms. This chapter discusses the building blocks of such computing systems, based on both embedded and superscalar processors, with different reliability (fault-tolerant) modes at the architecture layer to memories like caches, for heterogeneous in-order and out-of-order processors. We provide a comprehensive reliability, i.e., soft error, vulnerability analysis of different components in in-order and out-of-order processors, e.g., caches. We also discuss different methodologies to improve the performance and power of such a system by analyzing these vulnerabilities. Moreover, we show how such heterogeneous hardware-level hardening modes can further be complemented by software-level techniques that can be realized using a reliability-driven compiler (as introduced in Chapter “Dependable Software Generation and Execution on Embedded Systems”).

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Section: Run-time Systemmentioning

confidence: 99%

Section: Variability-aware Reliability-heterogeneous Processor [21]: mentioning

confidence: 99%

Fault-Tolerant Computing with Heterogeneous Hardening Modes

Kriebel

Khalid

Prabakaran

et al. 2020

Dependable Embedded Systems

Self Cite

View full text Add to dashboard Cite

show abstract

“…Salehi et al [21] on the hand propose a powerconstrained reliability Management System for darksilicon chips (dsReliM) which considers the reliability of tasks. The model of the system has been categorised into four different parts.…”

Section: Run-time Management Systemmentioning

confidence: 99%

“…This mode is selected for applications with low priority. Unlike [21], during this mode, the system operates at feasible V/F where thermal hotspots are considered as well as good performance.…”

Section: Run-time Management Systemmentioning

confidence: 99%

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

Ofori-Attah¹,

Wang²,

Agyeman³

2018

EAI Endorsed Transactions on Industrial Networks and Intelligen

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Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, with manycore integration set to be heading towards its thousands, power consumption and temperature increases per time, meaning the number of active nodes must be reduced drastically. Therefore, optimized techniques are demanded for continuous advancement in technology. Existing efforts try to overcome this challenge by activating nodes from different parts of the chip at the expense of communication latency. Other efforts on the other hand employ run-time power management techniques to manage the power performance of the cores trading-off performance for power. We found out that, for a significant amount of power to saved and high temperature to be avoided, focus should be on reducing the power consumption of all the on-chip components. Especially, the memory hierarchy and the interconnect. Power consumption can be minimized by, reducing the size of high leakage power dissipating elements, turning-off idle resources and integrating power saving materials.

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“…Rated peak power consumption predominantly determines the cost (and weight) of cooling infrastructure that accompanies the many-core. Higher peak power also results in higher on-chip temperatures, which leads to reliability issues [2][3][4]. Higher temperatures can also trigger performance crippling thermal-throttling, which makes execution unpredictable [5].…”

Section: Introductionmentioning

confidence: 99%

PkMin: Peak Power Minimization for Multi-Threaded Many-Core Applications

Maity

Pathania

Mitra

2020

JLPEA

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Multiple multi-threaded tasks constitute a modern many-core application. An accompanying generic Directed Acyclic Graph (DAG) represents the execution precedence relationship between the tasks. The application comes with a hard deadline and high peak power consumption. Parallel execution of multiple tasks on multiple cores results in a quicker execution, but higher peak power. Peak power single-handedly determines the involved cooling costs in many-cores, while its violations could induce performance-crippling execution uncertainties. Less task parallelization, on the other hand, results in lower peak power, but a more prolonged deadline violating execution. The problem of peak power minimization in many-cores is to determine task-to-core mapping configuration in the spatio-temporal domain that minimizes the peak power consumption of an application, but ensures application still meets the deadline. All previous works on peak power minimization for many-core applications (with or without DAG) assume only single-threaded tasks. We are the first to propose a framework, called PkMin, which minimizes the peak power of many-core applications with DAG that have multi-threaded tasks. PkMin leverages the inherent convexity in the execution characteristics of multi-threaded tasks to find a configuration that satisfies the deadline, as well as minimizes peak power. Evaluation on hundreds of applications shows PkMin on average results in 49.2% lower peak power than a similar state-of-the-art framework.

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dsReliM: Power-constrained reliability management in Dark-Silicon many-core chips under process variations

Cited by 20 publications

References 24 publications

Fault-Tolerant Computing with Heterogeneous Hardening Modes

Fault-Tolerant Computing with Heterogeneous Hardening Modes

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

PkMin: Peak Power Minimization for Multi-Threaded Many-Core Applications

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