DS-CDMA wired bus with simple interconnection topology for parallel processing system LSIs

Yoshimura, Ryuichi; Keat, Tan Boon; Ogawa, Takahiro; Hatanaka, Shingo; Matsuoka, Toshimasa; Taniguchi, Kenji

doi:10.1109/isscc.2000.839820

Cited by 35 publications

(18 citation statements)

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“…However, these architectures are based on fixed topologies, and therefore, are not fully optimized for traffic with time-varying characteristics. The use of sophisticated communication protocols [3], [6] and techniques for customizing these protocols, both statically and dynamically [7], [8], [9], have been proposed. Protocol and topology customization are complementary, and hence, may be combined to yield large performance gains.…”

Section: Related Workmentioning

confidence: 99%

FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology

Sekar¹,

Lahiri²,

Raghunathan³

et al. 2005

Proceedings. 42nd Design Automation Conference, 2005.

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In this paper, we describe FLEXBUS, a flexible, high-performance onchip communication architecture featuring a dynamically configurable topology. FLEXBUS is designed to detect run-time variations in communication traffic characteristics, and efficiently adapt the topology of the communication architecture, both at the system-level, through dynamic bridge by-pass, as well as at the component-level, using component re-mapping. We describe the FLEXBUS architecture in detail and present techniques for its run-time configuration based on the characteristics of the on-chip communication traffic. The techniques underlying FLEXBUS can be used in the context of a variety of on-chip communication architectures. In particular, we demonstrate its application to AMBA AHB, a popular commercial on-chip bus. Detailed experiments conducted on the FLEXBUS architecture using a commercial design flow, and its application to an IEEE 802.11 MAC processor design, demonstrate that it can provide significant performance gains as compared to conventional architectures (up to 31.5% in our experiments), with negligible hardware overhead.

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Section: Related Workmentioning

confidence: 99%

FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology

Sekar¹,

Lahiri²,

Raghunathan³

et al. 2005

Proceedings. 42nd Design Automation Conference, 2005.

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“…However, the nature of the summation prevents the result from being purely binary because the summed result can assume various values other than 1 or 0. To address this, [5] uses an analog capacitance bus in which values are represented by the charge amount stored in the capacitor. In [6], the values are represented by a multi-valued logic system.…”

Section: Cdma As a Multiprocessor Interconnect Strategymentioning

confidence: 99%

“…CDMA is a spreadspectrum technique which encodes information prior to transmission onto a communications medium, permitting simultaneous use of the medium by separate information streams. In [5][6], a multiple-valued CDMA scheme is examined as an interconnect for parallel processing systems. In [7], CDMA on a fiber-optic interconnect operating at 10 gigahertz speeds is proposed as a local area network interconnect.…”

Section: : Introductionmentioning

confidence: 99%

CDMA as a multiprocessor interconnect strategy

Bell

Kang

John³

et al. 2001

Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256)

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1: IntroductionHigh-performance servers are often implemented as shared-memory multiprocessor machines because of their flexibility in handling numerous data transactions simultaneously when transactions make use of data in orthogonal address spaces, while also efficiently supporting a coherency protocol when data is shared [1]. The performance of a shared-memory multiprocessor system often depends on the characteristics of the bus interconnect used to share data among the processors and memory modules in the system [1][2]. The ideal case is a fully-interconnected set of processors and memory modules. Interconnection between processors allows cache-to-cache transfers ("interventions") of modified data without waiting for memory access.However, the number of links in a fully-interconnected system grows proportionally to the square of the number of nodes [2]. In a VLSI environment using a synchronous bus interconnect, the number of pins and wires necessary to support a fully-connected bus structure becomes prohibitive. In addition, the increased number of connections lowers the overall yield of the interconnection and on-chip bus selection logic, thereby decreasing the overall faulttolerance of the system [3][4].When the network becomes something less than fullyinterconnected, such as in a ring or cube interconnect, the performance degrades because of the increasing pathlength of the communication between nodes [1]. Contention for fewer available communication points causes longer queueing delays. The bus utilization increases, and throughput suffers.Contention and queueing delays associated with processor interventions and memory access may prohibit the scalability of a multiprocessor system in which processors and memory share a common bus [1], generating diminishing performance returns as more processors are connected to the same bus structure. At the same time, the growing gap between processor speeds of over a gigahertz and synchronous interconnect speeds of a couple of hundred megahertz or less causes a larger percentage of system performance loss to be attributed to the memory subsystem and interconnect.There has been some recent interest in using high-bandwidth communications protocols to meet the interconnect needs of processing systems. One such technique is CodeDivision Multiple-Access (CDMA). CDMA is a spreadspectrum technique which encodes information prior to transmission onto a communications medium, permitting simultaneous use of the medium by separate information streams. In [5-6], a multiple-valued CDMA scheme is examined as an interconnect for parallel processing systems. In [7], CDMA on a fiber-optic interconnect operating at 10 gigahertz speeds is proposed as a local area network interconnect. In [8], CDMA is investigated as a means of more-fully interconnecting artificial neural network circuits since those circuits are known to suffer from a combinational explosion of nodes. The basic idea of these works is that pin counts and interconnect wiring can be drastically reduced by using ...

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“…An alternative way to increase the data rate of serial links is to encode the data to be transmitted in such a way that they are orthogonal to each other such that they can be conveyed to the same channel simultaneously and then recovered and separated at the receiver utilizing the intrinsic characteristics of orthogonality, as illustrated graphically in Fig. 1 [3][4][5][6][7][8]. Since this approach is based on the same principle as that of code-division-multiple-access (CDMA), a technology that is widely popular in wireless communications in handling multiple users that share the same wireless channel, it is henceforth termed CDMA serial links in this letter.…”

Section: Introductionmentioning

confidence: 99%

A new power-efficient CDMA-based transmitter for high-speed serial links

Al-Taee

Yuan

2012

Analog Integr Circ Sig Process

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Conventional CDMA serial links suffer from the drawback that the number of transmitters is limited to only two in practical implementations due to the reduced voltage spacing between adjacent logic states of the transmitted data. In this letter, we propose a new CDMA serial link architect that allows an arbitrary number of transmitters to transmit data over the same channel while keeping the voltage spacing between adjacent logic states of the transmitted data to be the same as that of 4 pulseamplitude-modulation serial link transmmitters. The effectiveness of the proposed architect is validated using the simulation results of a serial link with four transmitters designed in an IBM 130 nm 1.2 V CMOS technology.

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DS-CDMA wired bus with simple interconnection topology for parallel processing system LSIs

Cited by 35 publications

References 1 publication

FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology

FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology

CDMA as a multiprocessor interconnect strategy

A new power-efficient CDMA-based transmitter for high-speed serial links

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