DreamCam: A modular FPGA-based smart camera architecture

Birem, Merwan; Berry, François

doi:10.1016/j.sysarc.2014.01.006

Cited by 40 publications

(29 citation statements)

References 16 publications

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“…We have used the CAPH language and tool chain to implement various real-time stream-processing applications on FPGA-based boards, including in particular a smart-camera developed at our institute [3]. This smartcamera platform embeds a STRATIX EP1S60 FPGA, five 1MB SRAM banks and one 64MB SDRAM block.…”

Section: Resultsmentioning

confidence: 99%

“…An example of actor description in CAPH3 Pop the value from the connected FIFO.B. Describing valuesTwo kind of values can be exchanged by actors : built-in values and tagged (or constructed) values.Built-in values are those having a direct interpretation at the RT-level : signed and unsigned integers (with explicit size in bits), booleans, fixed-point and floating point values and arrays of built-in values.…”

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confidence: 99%

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High-Level Dataflow Programming for Reconfigurable Computing

Sérot

Berry

2014

2014 International Symposium on Computer Architecture and High Performance Computing Workshop

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In many application domains, FPGAs are now promoted as a way of getting round the restrictions of specific CPU designs on system scalability. However, in the current state-of-the art, programming FPGAs remains essentially a hardware-oriented activity, relying on dedicated hardware description languages such as VHDL or Verilog. Using these languages requires expertise in digital design and in practice this limits the applicability of FPGA-based solutions. This is particulary true for stream-processing applications, in which some processing must be carried out "on the fly" on digital data streams. In this context, the dataflow programming model offers a very effective way to reduce the gap between high-level formulations and low-level implementations. To support this claim, the authors have recently introduced CAPH, a domain specific language, offering a fully-automated compilation path from high-level dataflow descriptions to FPGA configuration for stream-processing applications. This paper is a introduction to the CAPH language, giving its motivations and main design principles and exposing the basic features of its syntax, semantics and compilation. It also points to experimental results showing that, at least for stream-processing applications, the dataflow model of computation, used jointly as a programming model and an execution model, can offer a very effective way to conciliate abstraction and efficiency when programming FPGAs.

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Section: Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

High-Level Dataflow Programming for Reconfigurable Computing

Sérot

Berry

2014

2014 International Symposium on Computer Architecture and High Performance Computing Workshop

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“…We assume that the in-built camera has the functionalities which can allow the driver to upload a given file or the camera’s sensors can decide to upload a particular video after analyzing abnormal movements within the video [49]. The timing and circumstances techniques in which the video should be uploaded are not within the scope of this paper.…”

Section: Details Of Proposed Protocolmentioning

confidence: 99%

Secure and Lightweight Cloud-Assisted Video Reporting Protocol over 5G-Enabled Vehicular Networks

Nkenyereye

Kwon

Choi

2017

Sensors

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In the vehicular networks, the real-time video reporting service is used to send the recorded videos in the vehicle to the cloud. However, when facilitating the real-time video reporting service in the vehicular networks, the usage of the fourth generation (4G) long term evolution (LTE) was proved to suffer from latency while the IEEE 802.11p standard does not offer sufficient scalability for a such congested environment. To overcome those drawbacks, the fifth-generation (5G)-enabled vehicular network is considered as a promising technology for empowering the real-time video reporting service. In this paper, we note that security and privacy related issues should also be carefully addressed to boost the early adoption of 5G-enabled vehicular networks. There exist a few research works for secure video reporting service in 5G-enabled vehicular networks. However, their usage is limited because of public key certificates and expensive pairing operations. Thus, we propose a secure and lightweight protocol for cloud-assisted video reporting service in 5G-enabled vehicular networks. Compared to the conventional public key certificates, the proposed protocol achieves entities’ authorization through anonymous credential. Also, by using lightweight security primitives instead of expensive bilinear pairing operations, the proposed protocol minimizes the computational overhead. From the evaluation results, we show that the proposed protocol takes the smaller computation and communication time for the cryptographic primitives than that of the well-known Eiza-Ni-Shi protocol.

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“…This simulation harness enables quick validation of image processing dataflow programs on CPUs. The functionality is implemented in the runtime system of Orcc's C backend, and is exposed as actors in the System project in the orc-apps library 1 . C. FPGA based System Architecture 1) Architecture Overview: The clean separation of subsystems allows power efficient application deployment across power islands: regions where different power modes (e.g., frequency scaling, power gating) can be applied independently.…”

Section: B Software Validation Of Image Processing Programsmentioning

confidence: 99%

“…Due to their decentralised local pre-processing smart cameras help to address the issues with traditional centralised camera networks, e.g., image communication over a resource limited (bandwidth and power) wireless network. A smart camera architecture (SCA) shifts pre-processing computations upstream to the source of image capture on dedicated, low powered embedded hardware [1]. Current available SCAs encounter problems due to a range of system-level design issues [2].…”

Section: Introductionmentioning

confidence: 99%

Power efficient dataflow design for a heterogeneous smart camera architecture

Bhowmik

Garcia

Wallace

et al. 2017

2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)

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Abstract-Visual attention modelling characterises the scene to segment regions of visual interest and is increasingly being used as a pre-processing step in many computer vision applications including surveillance and security. Smart camera architectures are an emerging technology and a foundation of security and safety frameworks in modern vision systems. In this paper, we present a dataflow design of a visual saliency based camera architecture targeting a heterogeneous CPU+FPGA platform to propose a smart camera network infrastructure. The proposed design flow encompasses image processing algorithm implementation, hardware & software integration and network connectivity through a unified model. By leveraging the properties of the dataflow paradigm, we iteratively refine the algorithm specification into a deployable solution, addressing distinct requirements at each design stage: from algorithm accuracy to hardware-software interactions, real-time execution and power consumption. Our design achieved real-time run time performance and the power consumption of the optimised asynchronous design is reported at only 0.25 Watt. The resource usages on a Xilinx Zynq platform remains significantly low.

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DreamCam: A modular FPGA-based smart camera architecture

Cited by 40 publications

References 16 publications

High-Level Dataflow Programming for Reconfigurable Computing

High-Level Dataflow Programming for Reconfigurable Computing

Secure and Lightweight Cloud-Assisted Video Reporting Protocol over 5G-Enabled Vehicular Networks

Power efficient dataflow design for a heterogeneous smart camera architecture

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