2016
DOI: 10.1007/s10766-016-0473-y
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DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool

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Cited by 12 publications
(2 citation statements)
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“…The NMC system is simulated with Ramulator-PIM [26] once, since the results do not vary in different runs. Power and time parameters for HMC are derived from [22], [27] and fed to the NMC simulator. As a benchmark, we selected a set of application from Polybench since it consists of simple mathematical operations extensively used in modern applications, and are also commonly used in NMC related work [28].…”
Section: Correct Predictions Total Number Of Predictionsmentioning
confidence: 99%
“…The NMC system is simulated with Ramulator-PIM [26] once, since the results do not vary in different runs. Power and time parameters for HMC are derived from [22], [27] and fed to the NMC simulator. As a benchmark, we selected a set of application from Polybench since it consists of simple mathematical operations extensively used in modern applications, and are also commonly used in NMC related work [28].…”
Section: Correct Predictions Total Number Of Predictionsmentioning
confidence: 99%
“…For eight layers, this adds up to 32Gb, thus allowing 32 H-Cubes. The timing, current, and area values of the presented custom 3D DRAM for the 28 nm process with the TSV pitch of 40 μm are extracted from DRAMSpec [20,21], and the exact area dimension of each H-Cube is shown in Fig. 8.…”
Section: Dimensioning the Bcumentioning
confidence: 99%