DRAMA: An Architecture for Accelerated Processing Near Memory

Farmahini-Farahani, Amin; Ahn, Jung Ho; Morrow, Katherine; Kim, Nam Sung

doi:10.1109/lca.2014.2333735

Cited by 38 publications

(22 citation statements)

References 11 publications

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“…al. (FARMAHINI-FARAHANI et al, 2014) proposed an architecture that consists of a Coarse-Grain Reconfigurable Array (CGRA) placed atop a stack of DRAM modules. The mechanism aims to accelerate scientific and embedded applications.…”

Section: The Systemc Programming Modelmentioning

confidence: 99%

A generic processing in memory cycle accurate simulator under hybrid memory cube architecture

Oliveira

Santos

Alves

et al. 2017

2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

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PIM-a technique which computational elements are added close, or ideally, inside memory devices-was one of the attempts created during the 1990s to try to mitigate the memory wall problem. Nowadays, with the maturation of 3D integration technologies, a new landscape for novel PIM architectures can be investigated. To exploit this new scenario, researchers rely on software simulators to navigate throughout the design evaluation space. Today, most of the works targeting PIM implement in-house simulators to perform their experiments. However, this methodology might hurt overall productivity, while it might also preclude replicability. In this work, we showed the development of a precise, modular and parametrized PIM simulation environment. Our simulator, named CLAPPS, targets the HMC architecture, a popular 3D-stacked memory widely employed in state-of-the-art PIM accelerators. We have designed our mechanism using the SystemC programming language, which allows native parallel simulation. The primary contribution of our work lies in developing a user-friendly interface to allow easy PIM architectures exploitation. To evaluate our system, we have implemented a PIM module that can perform vector operations with different operand sizes using the proposed set of tools.

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Section: The Systemc Programming Modelmentioning

confidence: 99%

A generic processing in memory cycle accurate simulator under hybrid memory cube architecture

Oliveira

Santos

Alves

et al. 2017

2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

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“…Faramahini et al [58] presented a technique, which improves the cache power consumption. The SRAM is placed closer to memory rather than closer to the processor.…”

Section: Techniquesmentioning

confidence: 99%

Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer

Ofori-Attah

Bhebhe

Agyeman

2017

JLPEA

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The disparity between memory and CPU have been ameliorated by the introduction of Network-on-Chip-based Chip-Multiprocessors (NoC-based CMPS). However, power consumption continues to be an aggressive stumbling block halting the progress of technology. Miniaturized transistors invoke many-core integration at the cost of high power consumption caused by the components in NoC-based CMPs; particularly caches and routers. If NoC-based CMPs are to be standardised as the future of technology design, it is imperative that the power demands of its components are optimized. Much research effort has been put into finding techniques that can improve the power efficiency for both cache and router architectures. This work presents a survey of power-saving techniques for efficient NoC designs with a focus on the cache and router components, such as the buffer and crossbar. Nonetheless, the aim of this work is to compile a quick reference guide of power-saving techniques for engineers and researchers.

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“…Faramahini et al [25] use a technique called Near-Memory Caching for improved energy consumption. The SRAM is placed closer to memory rather than closer to the processor.…”

Section: Overviewmentioning

confidence: 99%

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

Bhebhe

Agyeman

2016

CAE

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Abstract-The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity between the CPU performance and storage. There are encouraging breakthroughs in enhancing CPU performance through fabrication technologies and changes in chip designs but not as much luck has been struck with regards to the computer storage resulting in material negative system performance. A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures. This work is a survey of energy saving techniques which are grouped on whether they save the dynamic energy, leakage energy or both. Needless to mention, the aim of this work is to compile a quick reference guide of energy saving techniques from 2013 to 2016 for engineers, researchers and students.

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DRAMA: An Architecture for Accelerated Processing Near Memory

Cited by 38 publications

References 11 publications

A generic processing in memory cycle accurate simulator under hybrid memory cube architecture

A generic processing in memory cycle accurate simulator under hybrid memory cube architecture

Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

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