Drain current model for undoped Gate Stack Double Gate (GSDG) MOSFETs including the hot-carrier degradation effects

Djeffal, F.; Bentrcia, Toufik; Abdi, M.A.; Bendib, T.

doi:10.1016/j.microrel.2010.10.002

Cited by 24 publications

(8 citation statements)

References 14 publications

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“…Those parameters are basically based on fitted data on the fabricated NVM devices [42][43][44][45]. In order to avoid degradation of the memory performance such as the hot carrier effect [46,47], the very high voltage was applied to the gate electrode utilizing Fowler-Nordheim (FN) tunneling and the drain voltage for read operation is relatively low (~1 V). For the memory operation, the programming and erasing voltages are 18 and −18 V, respectively.…”

Section: Memory Characteristics Of the M3d-nvm-fbfetmentioning

confidence: 99%

Investigation of the Electrical Coupling Effect for Monolithic 3-Dimensional Nonvolatile Memory Consisting of a Feedback Field-Effect Transistor Using TCAD

Oh,

2023

Micromachines

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In this study, the electrical characteristics and electrical coupling effect for monolithic 3-dimensional nonvolatile memory consisting of a feedback field-effect transistor (M3D-NVM-FBFET) were investigated using technology computer-aided design. The M3D-NVM-FBFET consists of an N-type FBFET with an oxide–nitride–oxide layer and a metal–oxide–semiconductor FET (MOSFET) in the top and bottom tiers, respectively. For the memory simulation, the programming and erasing voltages were applied at 18 and −18 V for 1 μs, respectively. The memory window of the M3D-NVM-FBFET was 1.98 V. As the retention simulation was conducted for 10 years, the memory window decreased from 1.98 to 0.83 V. For the M3D-NVM-FBFET, the electrical coupling that occurs through an electrical signal in the bottom-tier transistor was investigated. As the thickness of the interlayer dielectric (TILD) decreases from 100 to 10 nm, the change in the VTH increases from 0.16 to 0.87 V and from 0.15 to 0.84 V after the programming and erasing operations, respectively. M3D-NVM-FBFET circuits with a thin TILD of 50 nm or less need to be designed considering electrical coupling.

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Section: Memory Characteristics Of the M3d-nvm-fbfetmentioning

confidence: 99%

Investigation of the Electrical Coupling Effect for Monolithic 3-Dimensional Nonvolatile Memory Consisting of a Feedback Field-Effect Transistor Using TCAD

Oh,

2023

Micromachines

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“…The graphene and SiO 2 oxide interface can also degrade the performance of the device due to the mismatch of structure and tunneling of hot electrons into the oxide [20]. It leads to the degradation of drain current (I d ) and V th .…”

Section: Literature Reviewmentioning

confidence: 99%

Implementation of 20 nm Graphene Channel Field Effect Transistors Using Silvaco TCAD Tool to Improve Short Channel Effects over Conventional MOSFETs

Tayade

Lahudkar²

2021

Adv. technol. innov.

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In recent years, demands for high speed and low power circuits have been raised. As conventional metal oxide semiconductor field effect transistors (MOSFETs) are unable to satisfy the demands due to short channel effects, the purpose of the study is to design an alternative of MOSFETs. Graphene FETs are one of the alternatives of MOSFETs due to the excellent properties of graphene material. In this work, a user-defined graphene material is defined, and a graphene channel FET is implemented using the Silvaco technology computer-aided design (TCAD) tool at 100 nm and scaled to 20 nm channel length. A silicon channel MOSFET is also implemented to compare the performance. The results show the improvement in subthreshold slope (SS) = 114 mV/dec, ION/IOFF ratio = 14379, and drain induced barrier lowering (DIBL) = 123 mV/V. It is concluded that graphene FETs are suitable candidates for low power applications.

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“…The analytical formulation for uniformly doped DG MOSFET has already been available in the literature [3]- [5]. However, the doping impurities may get alter after thermal annealing or during other fabrication process steps thereby showing gaussian doping along the channel instead of uniform doping.…”

Section: Introductionmentioning

confidence: 99%

Modeling and Simulation of Nanoscale Lateral Gaussian Doped Channel Asymmetric Double Gate MOSFET

Kumari

Saxena

Gupta

2015

JNanoR

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This work presents the drain current model using Evanescent Mode Analysis (EMA) for nanoscale Double Gate MOSFET having Gaussian doping profile along the horizontal direction in the channel i.e. from source to drain region. Due to heavily doped channel, band gap narrowing effect is incorporated in the analytical modeling scheme. The various parameters evaluated in this work using analytical modeling scheme are surface potential, electric field, threshold voltage, sub-threshold slope and drain current. The impact of peak Gaussian doping profile on the drain current and trans-conductance has been demonstrated which are important for assessing the analog performance of the device. The results are also compared with the uniformly doped DG MOSFET. The asymmetric behaviour of Gaussian doped DG MOSFET has also been investigated. In addition to this, digital performance of Gaussian doped DG MOSFET has also been assessed using exhaustive device simulation.

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Drain current model for undoped Gate Stack Double Gate (GSDG) MOSFETs including the hot-carrier degradation effects

Cited by 24 publications

References 14 publications

Investigation of the Electrical Coupling Effect for Monolithic 3-Dimensional Nonvolatile Memory Consisting of a Feedback Field-Effect Transistor Using TCAD

Investigation of the Electrical Coupling Effect for Monolithic 3-Dimensional Nonvolatile Memory Consisting of a Feedback Field-Effect Transistor Using TCAD

Implementation of 20 nm Graphene Channel Field Effect Transistors Using Silvaco TCAD Tool to Improve Short Channel Effects over Conventional MOSFETs

Modeling and Simulation of Nanoscale Lateral Gaussian Doped Channel Asymmetric Double Gate MOSFET

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