DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs

Grycel, Jacob T.; Walls, Robert J.

doi:10.1109/iscas45731.2020.9181186

Cited by 2 publications

(4 citation statements)

References 6 publications

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“…At the same time, our throughput value is slightly less but comparable to Hybrid AES model 25 implement AES on Virtex-7 hardware. Research work 20 is implemented using DRAB-LOCUS Architecture on ZynQ7000 and produces an optimized throughput of 7.055 Gbps, simultaneously consuming lesser area. Our Work-MDP1 gives a better result comparatively when implemented on the same hardware.…”

Section: Resultsmentioning

confidence: 99%

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Low area and high throughput implementation of advanced encryption standard hardware accelerator on FPGA using Mux‐Demux pair

Renugadevi

Julakanti

Vemula³

et al. 2022

Security and Privacy

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Now‐a‐days advanced cryptographic algorithms are needed in order to improve data security and confidentiality. One such algorithm used prominently is advanced encryption standard (AES) algorithm. AES is a complex algorithm with multiple rounds of processing data and occupies more space or area when implemented on hardware. Since each sub‐step of computation has a similar structure, the proposed method employs the novel idea of using the same hardware to implement the AES functionality. Hence the number of logical units occupied are leveraged. The proposed scheme, Mux‐Demux pair method (MDP), uses a mux‐demux structure. It is implemented on Virtex‐7 and ZynQ7000 FPGAs and the code is written in Verilog HDL language in the Vivado software. The proposed work when simulated on Virtex‐7 occupies an area of 1932 slices, giving an optimized throughput of 10.167 Gbps while the work simulated on ZynQ7000 occupies an area of 3253 slices, resulting in a throughput of 23.858 Gbps.

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Section: Resultsmentioning

confidence: 99%

“…In the study by Grycell and Walls in Reference 20, the shared resource challenge has been addressed with the main goal being reduction of area and enhancement of throughput. Digital Signal Processing slices have been designed to implement various processes in each round.…”

Section: Literature Reviewmentioning

confidence: 99%

Low area and high throughput implementation of advanced encryption standard hardware accelerator on FPGA using Mux‐Demux pair

Renugadevi

Julakanti

Vemula³

et al. 2022

Security and Privacy

View full text Add to dashboard Cite

show abstract

“…They achieved an increase in memory access of three times more compared to standard hardware. In a study by Grycell and Walls in Reference 42 they have addressed the shared resource challenge and also achieved less area and high throughput. They have used Digital Signal Processing slices to implement various processes in a round.…”

Section: Literature Reviewmentioning

confidence: 99%

“…The masking execution of S‐box in Reference 17 increased the security against side‐channel attacks; however, it reduced the throughput by 1.6 times compared to the unmasked technique. The proposed method in Reference 42 uses the DRAB‐LOCUS technique, thus producing a throughput of 7.055Gbps and reduced area when implemented on ZynQ 7000. In the article, 29 a multi‐core AES was implemented using CMOS technology of 45 nm.…”

Section: Comparison On Different Evaluation Metricsmentioning

confidence: 99%

Methods for improving the implementation of advanced encryption standard hardware accelerator on field programmable gate array‐A survey

Renugadevi

Thangallapally²,

Vemula³

et al. 2022

Security and Privacy

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With the majority of users migrating to a cloud computing platform, the responsibility for data security has increased considerably. As data with various levels of sensitivity moves out of the confines of the system firewall, there is no control over where it resides; it depends on the cloud server being used. This makes the use of secured cryptographic algorithms necessary to improve data security and maintain the confidentiality of data. The encryption algorithm used most extensively today is the Advanced Encryption Standard (AES). Hardware acceleration with Field Programmable Gate Array can improve the performance of AES. This study examines various approaches for improving data encryption methods that can be utilized as hardware accelerators to improve the fundamental AES cipher. Some research publications suggest ways to boost throughput while others advise ways to save area and power. Many subsequent developments have also used other cryptographic methods such as RSA and ECC to improve key management security. This study examines the outcomes of multiple ways for metrics including throughput, area, power, and data security, and explains some of the best implementation solutions for each metric individually.

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DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs

Cited by 2 publications

References 6 publications

Low area and high throughput implementation of advanced encryption standard hardware accelerator on FPGA using Mux‐Demux pair

Low area and high throughput implementation of advanced encryption standard hardware accelerator on FPGA using Mux‐Demux pair

Methods for improving the implementation of advanced encryption standard hardware accelerator on field programmable gate array‐A survey

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