DPA: A data pattern aware error prevention technique for NAND flash lifetime extension

Guo, Jie; Chen, Zhijie; Wang, Danghui; Shao, Zili; Chen, Yiran

doi:10.1109/aspdac.2014.6742955

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Nand Flash Noise and Eccs1

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Cited by 23 publications

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“…Cell-to-cell interference and retention time limit are two major contributors to bit errors in NAND flash memory [7,8].…”

Section: Nand Flash Noise and Eccsmentioning

confidence: 99%

FlexLevel

Guo

Wen

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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LDPC code is introduced in NAND flash memory to handle high BER (bit error rate) incurred by technology scaling. Despite strong error correction capability, LDPC decoding induces long NAND flash read latency. In this work, we propose FlexLevel -a robust NAND flash storage system design to improve data reliability and read efficiency affected by the LDPC operations. FlexLevel first reduces BER by enlarging noise margins via V th (threshold voltage) level reduction. It reduces the sensing levels of LDPC but also causes loss of storage capacity. To compensate this capacity loss with minimum impact on read performance, FlexLevel identifies the data with high LDPC overhead and only applies the V th level reduction technique to those data. Experimental results show that compared with state-of-the-art, FlexLevel can achieve up to 33% read speedup with very moderate capacity loss.

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“…Cell-to-cell interference and retention time limit are two major contributors to bit errors in NAND flash memory [7,8].…”

Section: Nand Flash Noise and Eccsmentioning

confidence: 99%