Reliability issues are very important especially for the highvoltage (HV) devices. Unfortunately, an HV nLDMOS is often damaged by a latch-up (LU) problem when it triggered by a transient noise and a bias condition VDDmax is greater than that of the device holding-voltage (Vh). The snapback phenomena of the new adding adaptive layers in the source/drain ends of an nLDMOS are investigated in this paper. It is a novel method to reduce the surface field, control the trigger voltage and holding voltage. Experimentally, the right-shifting characteristic of snapback I-V curves depends on new adding Pad, LPad, Nad, and LNad parameters, respectively. Eventually, these source/drain adaptive layers of an nLDMOS can effectively improve the LU immunity under an HV operation.