Double-least-significant-bits 2's-complement number representation scheme with bitwise complementation and symmetric range

Abstract

A scheme is proposed for representing 2's-complement binary numbers in which there are two least-significant bits (LSBs). Benefits of the extra LSB include making the number representation range symmetric (i.e. from 22 k21 to 2 k21 for k-bit integers), allowing sign change by simple bitwise logical inversion, facilitating multiprecision arithmetic and enabling the truncation of results in lieu of rounding. These advantages justify the added storage and interconnect costs stemming from the extra bit. Operation latencies show little or no change relative to conventional 2's-complement arithmetic, thus making double-LSB representation attractive.

Energy‐efficient VLSI implementation of multipliers with double LSB operands

“…Both theoretical and robust experimental evaluations on industrialstrength tools are provided. We show that our design outperforms the previous implementation proposed in [6], as it delivers a smaller overhead in comparison with the conventional Modified Booth (CMB) multiplier [10].…”

“…The previous DLSB multiplication scheme based on the Modified Booth encoding was proposed by Parhami [6]. More explicitly, using (2) and 3, the product is given by the next relation…”

“…In our design, the depth of the Wallace tree is the same with CMB, and hence, negligible or zero circuit delay is added. In contrast, DLSB [6] additionally accumulates the row that implements a 0 + ⋅ (⟨b n − 1 b n − 2 ⋯b 0 ⟩ 2′s + b 0 + ). Hence, the proposed design consists of a CMB multiplier, with an overhead of only n/2 XOR-2 gates for calculating s j ′ = b 2 j + 1 ⊕ a 0 + = s j ⊕ a 0 + , a term used in the computation of p j, 0 ′ and c in, j ′ ((16) and (17), respectively).…”

“…Moreover, the area of a Full Adder (FA) and a Half Adder (HA) is 7 and 3 unit gates, respectively. All the information above, along with the gate equivalence of the circuits used in the partial product generation of CMB, proposed DLSB and DLSB [6], are summarised in Table 2. The n × n bit multiplier generates n/2 (n + 1)-bit partial products. Therefore, n/2 encoders, n/2 × (n + 1) partial product generators, and n/2 carry input generators are required.…”

A modulo 2ⁿ+1 multiplier with double-LSB encoding of residues

“…Both schemes hav e special provisions, bearing additional complexity, for handling the end-around carry. Double-Isb encoding [16] of modulo 2 n +I residues has been used in the design of a modulo 2 n +I adder [17], where each operand is represented by a normal n-bit number that is augmented with a second least significant bit (LSB). This encoding provides a faithful representation, where there would be no code word that evaluates to a number out of the valid range [0, 2 n ] .…”