Dopant profiling in ultrathin silicon-on-insulator layers

Abstract

Low-energy B, BF 2 , and As implants into 20 nm, 50 nm, and 150 nm Si layers on silicon-on-insulator wafers were investigated. Before annealing, a pileup of the B and As was observed at the Si/buried oxide interface in samples where the implant range and straggle approached the Si layer thickness. The absence of 10 B from the interface, along with the presence of the pileup in profiles obtained from the back side of the samples, indicates that the pileup is implant induced. The pileup is believed to be due to the blockage of the open channels in the single-crystal Si by the amorphous SiO 2 at the interface. In samples pre-amphorized with Ge the pileup is not observed. Examples of representative profiles will be presented along with a discussion of the methods used to reduce or eliminate several secondary ion mass spectrometry artifacts.

Front and back side Auger electron spectroscopy depth profile analysis to verify an interfacial reaction at the HfN∕SiO2 interface

“…[7][8][9] The use of combined front and back side AES depth profiling is presented here as a method to help distinguish interfacial chemistry due to sputter-induced artifacts from native interfacial chemistry. [7][8][9] The use of combined front and back side AES depth profiling is presented here as a method to help distinguish interfacial chemistry due to sputter-induced artifacts from native interfacial chemistry.…”