Dominant edge direction based fast intra mode decision in the H.264/AVC encoder

La, Byeongdu; Eom, Minyoung; Choe, Yoonsik

doi:10.1631/jzus.a0820473

Cited by 3 publications

(1 citation statement)

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“…The H.264/AVC Advanced Video Coding standard (AVC) provides high-quality coding of video contents at very low bit rates relative to the former video compression standards [1][2][3]. The compression quality is achieved by adding a number of new compression techniques including spatial intraprediction, (4 × 4) integer transform, multiple reference frames, multiple block sizes for interframe coding, quarter pixel motion estimation (ME), deblock filtering, and content-adaptive arithmetic coding [4][5][6]. These additional features and functionalities improve the coding efficiency at the cost of a significant increase in computational complexity [3,5,7].…”

Section: Introductionmentioning

confidence: 99%

A Hybrid Scheme Based on Pipelining and Multitasking in Mobile Application Processors for Advanced Video Coding

Asif

Taj

Ziauddin

et al. 2015

Scientific Programming

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One of the key requirements for mobile devices is to provide high-performance computing at lower power consumption. The processors used in these devices provide specific hardware resources to handle computationally intensive video processing and interactive graphical applications. Moreover, processors designed for low-power applications may introduce limitations on the availability and usage of resources, which present additional challenges to the system designers. Owing to the specific design of the JZ47x series of mobile application processors, a hybrid software-hardware implementation scheme for H.264/AVC encoder is proposed in this work. The proposed scheme distributes the encoding tasks among hardware and software modules. A series of optimization techniques are developed to speed up the memory access and data transferring among memories. Moreover, an efficient data reusage design is proposed for the deblock filter video processing unit to reduce the memory accesses. Furthermore, fine grained macroblock (MB) level parallelism is effectively exploited and a pipelined approach is proposed for efficient utilization of hardware processing cores. Finally, based on parallelism in the proposed design, encoding tasks are distributed between two processing cores. Experiments show that the hybrid encoder is 12 times faster than a highly optimized sequential encoder due to proposed techniques.

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