Doing more with less - An IEEE 1149.7 embedded tutorial : Standard for reduced-pin and enhanced-functionality test access port and boundary-scan architecture

Ley, Adam W

doi:10.1109/test.2009.5355572

Cited by 11 publications

(2 citation statements)

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“…In addition to allowing serial connection of multiple cores, the standard introduces two‐wire and four‐wire star configurations. As described by Ley [26] this standard is of particular benefit for SoC or system‐in‐package designs. Enhancements such as: reducing I/O to just two pins, using a star topology, the concept of 1149.7 being an ‘adaptor’ for existing 1149.1 TAPs, and the introduction of hierarchy, ease integration challenges.…”

Section: Standard Interfacesmentioning

confidence: 99%

On‐chip support for software verification and debug in multi‐core embedded systems

2013

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The challenges in silicon testing and debug of complex integrated circuits are well understood. Where these circuits include multiple processor cores there is also a dramatic increase in the complexity of verifying and debugging the associated software; with much of this complexity being because of the inherent lack of visibility over internal signals which integration brings. The trend to-date has been to rely upon silicon test interfaces to provide access to internal signals required for software verification and debug. However, it is questionable whether this is sufficient for real-time systems or future designs with increasing processor cores. This study examines the on-chip technology supporting software verification and debug in current designs and proposes enhancements in this area. As much of this technology is primarily intended for silicon test it is lacking in terms of I/O bandwidth, which is a significant limitation for software verification and debug. The authors propose their alternative approach of using an on-chip coprocessor and debug circuitry to address this principal limitation; and describe an embedded application where this approach was successfully applied to monitor timing requirements and detect failures. The authors also outline how this approach could be applied as an architectural solution for formal runtime verification.

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Section: Standard Interfacesmentioning

confidence: 99%

On‐chip support for software verification and debug in multi‐core embedded systems

2013

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“…In recognition of the need for a more powerful test standard, compatible with all the investment made in 1149.1, the IEEE 1149.7 Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture was approved in 2009 [2], and offered a far more powerful solution to test and applications debug. The development of solutions that demonstrate its ability to coexist with 1149.1 applications, while at the same time supporting the more powerful scan transfer formats required for debugging multi-core architectures, represents a fundamental step to unlock the power of the new standard and to promote its wider acceptance [3]- [5]. This paper presents a microprogrammed architecture for an embedded coprocessor dedicated to IEEE 1149.1/ 1149.7 test operations.…”

Section: Introductionmentioning

confidence: 99%

An IEEE 1149.x Embedded Test Coprocessor

Gebremeskel¹,

Ferreira²

2014

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This paper describes a microprogrammed architecture for an embedded coprocessor that is able to control IEEE 1149.1 to IEEE 1149.7 test infrastructures, and explains how to expand the supported test command set. The coprocessor uses a fast simplex link (FSL) channel to interface a 32-bit MicroBlaze CPU, but it can work with any microprocessor core that accepts this simple FIFO-based interface method. The implementation cost (logic resource usage for a Xilinx Spartan-6 FPGA) and the performance data (operating frequency) are presented for a test command set comprising two parts: 1) the full IEEE 1149.1 structural test operations; 2) a subset of IEEE 1149.7 operations selected to illustrate the implementation of advanced scan formats.

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