DMNI: A specialized network interface for NoC-based MPSoCs

Ruaro, Marcelo; Lazzarotto, Felipe B.; Marcon, César; Moraes, Fernando

doi:10.1109/iscas.2016.7527462

Cited by 20 publications

(13 citation statements)

References 12 publications

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“…The efficiency of the proposed at higher number of PE shows divergence from ideal speedup, this trend can be improved by the use of efficient communication interface such as Network-on-Chip (NoC) for linking of multiple cores. Researchers have provided various platforms for NoC based MPSoC models [39,40]. The use of NoC in multicore models in various application has shown promising results in terms of scalability and efficiency [14,41,42,43,44,45].…”

Section: Experimentation and Resultsmentioning

confidence: 99%

A Parallel Architecture for the Partitioning around Medoids (PAM) Algorithm for Scalable Multi-Core Processor Implementation with Applications in Healthcare

Mushtaq

Khawaja

Akram

et al. 2018

Sensors

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Clustering is the most common method for organizing unlabeled data into its natural groups (called clusters), based on similarity (in some sense or another) among data objects. The Partitioning Around Medoids (PAM) algorithm belongs to the partitioning-based methods of clustering widely used for objects categorization, image analysis, bioinformatics and data compression, but due to its high time complexity, the PAM algorithm cannot be used with large datasets or in any embedded or real-time application. In this work, we propose a simple and scalable parallel architecture for the PAM algorithm to reduce its running time. This architecture can easily be implemented either on a multi-core processor system to deal with big data or on a reconfigurable hardware platform, such as FPGA and MPSoCs, which makes it suitable for real-time clustering applications. Our proposed model partitions data equally among multiple processing cores. Each core executes the same sequence of tasks simultaneously on its respective data subset and shares intermediate results with other cores to produce results. Experiments show that the computational complexity of the PAM algorithm is reduced exponentially as we increase the number of cores working in parallel. It is also observed that the speedup graph of our proposed model becomes more linear with the increase in number of data points and as the clusters become more uniform. The results also demonstrate that the proposed architecture produces the same results as the actual PAM algorithm, but with reduced computational complexity.

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Section: Experimentation and Resultsmentioning

confidence: 99%

A Parallel Architecture for the Partitioning around Medoids (PAM) Algorithm for Scalable Multi-Core Processor Implementation with Applications in Healthcare

Mushtaq

Khawaja

Akram

et al. 2018

Sensors

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“…In the proposed approach, it is likely that the NI will have to use the local memory tile to store the ejected flits. Such integration of the NI with the memory controller of the local tile has already been investigated in [26], enabling direct memory access from incoming flits from the router as required in change 4. In our approach, however, it is possible that multiple flits can be ejected (i.e.…”

Section: Proposed Flow Control Protocolmentioning

confidence: 99%

“…As mentioned in Section III when we discussed the introduction of change 4, the NI will often have to use the memory of the local tile as temporary storage of ejected flits for the second assumption to hold (unless the number of ejected flits is small enough to fit in NI buffers, which we assume to be the exception rather than the rule). In the case of routers with a single sink (which would be the most common scenario, as shown in Section V), the access to the tile memory could be solved with a NI design such as the one presented in [26]. For the cases where multiple sinks are needed, the problem becomes more complex as multiple ejected flits arriving to the NI at each cycle may require tile memory to support multiple simultaneous reads and writes, or require the tile to operate at a faster frequency than the network.…”

Section: Limitations and Future Workmentioning

confidence: 99%

A Novel Flow Control Mechanism to Avoid Multi-Point Progressive Blocking in Hard Real-Time Priority-Preemptive NoCs

Burns

Indrusiak

Smirnov

et al. 2020

2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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The recently uncovered problem of multi-point progressive blocking (MPB) has significantly increased the complexity of schedulability analysis of priority-preemptive wormhole networks-on-chip. While state-of-the-art analysis is currently deemed safe, there is still significant inherent pessimism when it comes to considering backpressure issues caused by downstream indirect interference. In this paper, we attempt to simplify the problem by considering a novel flow control protocol that can avoid backpressure issues, enabling simpler schedulability analysis approaches to be used. Rather than construct the analysis to fit the protocol, we modify the protocol so that effective analysis applies. We describe the changes to a baseline wormhole router in order to implement the proposed protocol, and comment on the impact on hardware overheads. We also examine the number of routers that actually require these changes. Comparative analysis of FPGA implementations show that the hardware overheads of the proposed NoC router are comparable or lower than those of the baseline, while analytical comparison shows that the proposed approach can guarantee schedulability in up to 77% more cases.

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“…As mentioned before, a 2D mesh-style NoC that uses a credit-based flow control with the XY routing scheme was selected as system interconnect. Our NoC implementation is based on the work presented in [16] with some adaptions made especially to the direct memory network interface (DMNI) [17] which is responsible for managing the data flow between the processing cores and the NoC. One possible configuration of the interconnect is shown in Fig.…”

Section: A System Overviewmentioning

confidence: 99%

“…DMANI: The DMANI used in this work is an extension of the DMNI introduced in [17] whose main task is to offload the NoC packet-handling from the processing core so that said core can focus on performing computations. While the original DMNI required the accelerator to set up every NoC packet, containing information such as the target address and payload size, our DMANI does this on its own.…”

Section: Network-on-chip Componentsmentioning

confidence: 99%

Dataflow Aware Mapping of Convolutional Neural Networks Onto Many-Core Platforms With Network-on-Chip Interconnect

Bytyn,

Ahlsdorf,

Leupers

et al. 2020

Preprint

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Machine intelligence, especially using convolutional neural networks (CNNs), has become a large area of research over the past years. Increasingly sophisticated hardware accelerators are proposed that exploit e.g. the sparsity in computations and make use of reduced precision arithmetic to scale down the energy consumption. However, future platforms require more than just energy efficiency: Scalability is becoming an increasingly important factor. The required effort for physical implementation grows with the size of the accelerator making it more difficult to meet target constraints. Using many-core platforms consisting of several homogeneous cores can alleviate the aforementioned limitations with regard to physical implementation at the expense of an increased dataflow mapping effort. While the dataflow in CNNs is deterministic and can therefore be optimized offline, the problem of finding a suitable scheme that minimizes both runtime and off-chip memory accesses is a challenging task which becomes even more complex if an interconnect system is involved. This work presents an automated mapping strategy starting at the single-core level with different optimization targets for minimal runtime and minimal off-chip memory accesses. The strategy is then extended towards a suitable many-core mapping scheme and evaluated using a scalable system-level simulation with a network-on-chip interconnect. Design space exploration is performed by mapping the well-known CNNs AlexNet and VGG-16 to platforms of different core counts and computational power per core in order to investigate the trade-offs. Our mapping strategy and system setup is scaled starting from the single core level up to 128 cores, thereby showing the limits of the selected approach.

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DMNI: A specialized network interface for NoC-based MPSoCs

Cited by 20 publications

References 12 publications

A Parallel Architecture for the Partitioning around Medoids (PAM) Algorithm for Scalable Multi-Core Processor Implementation with Applications in Healthcare

A Parallel Architecture for the Partitioning around Medoids (PAM) Algorithm for Scalable Multi-Core Processor Implementation with Applications in Healthcare

A Novel Flow Control Mechanism to Avoid Multi-Point Progressive Blocking in Hard Real-Time Priority-Preemptive NoCs

Dataflow Aware Mapping of Convolutional Neural Networks Onto Many-Core Platforms With Network-on-Chip Interconnect

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