Divide‐by‐2 LC injection‐locked frequency divider with wide locking range at low and high injection powers

This paper presents power and area optimized, high-speed metal-oxidesemiconductor (MOS) current mode logic (MCML)-based frequency dividers. Each differential pair in the divider is sized separately to minimize the overall power consumption. The divide-by-2 frequency divider has been realized in a 180-nm complementary MOS (CMOS) process technology, and postlayout simulation results show that the proposed frequency divider can work up to an operating frequency of 18.8 GHz in the worst-case process corner with a maximum power dissipation of 1.715 mW under 1.8-V supply. It gives a bandwidth of 19.9 GHz which ranges from 1 to 20.9 GHz. The divider occupies a 0.106 Â 0.09 mm 2 area. The performance corresponds to the figure of merit (FoM) of 43.61 dB. The same optimized latches and two EX-OR gates are used to design a divide-by-5 frequency divider that is also realized in 180-nm CMOS process technology. The postlayout simulation results show that the proposed divide-by-5 frequency divider can faithfully work up to an operating frequency of 12.12 GHz in worst-case process corner with an excellent power head performance. The maximum power dissipation of the core circuit is 1.39 mW under 1.8-V supply. It occupies a 0.166 Â 0.116 mm 2 area. The performance corresponds to the FoM of 26.56 dB which compares favorably with the state of the art.

Section: Introductionmentioning

confidence: 99%

Power and area‐efficient static current mode logic frequency divider in 180‐nm complementary metal‐oxide‐semiconductor technology

Maity

Jana

Som

et al. 2021

“…They are based on locking a low‐frequency oscillator to an incoming signal at its n th harmonic. They are classified as divide‐by‐even number and divide‐by‐odd ILFDs . Divide‐by‐5 ILFD is one of the divide‐by‐odd number ILFDs aimed to reduce RF power consumption and circuit complexity.…”

Section: Introductionmentioning

confidence: 99%

Wide‐band dual‐resonance capacitive cross‐coupled divide‐by‐5 injection‐locked frequency divider

Jang

Huang

2017

Self Cite

Summary A wide locking range divide‐by‐5 injection‐locked frequency divider (ILFD) is proposed and was implemented in the TSMC 0.18‐μm 1P6M CMOS process. Conventional divide‐by‐5 ILFD has limited locking range. The proposed divide‐by‐5 ILFD is based on a capacitive cross‐coupled voltage‐controlled oscillator (VCO) with a dual‐resonance resonator, which is implemented in the divide‐by‐5 ILFD to obtain a wide overlapped locking range. At the drain‐source bias VDD of 0.9 V and at the incident power of 0 dBm, the measured locking range of the divide‐by‐5 ILFD is 3.2 GHz, from the incident frequency 9.4 to 12.6 GHz, the percentage is 29.09%. The core power consumption is 2.98 mW. The die area is 0.987 × 1.096 mm2.

Design and analysis of a millimeter‐wave injection locked frequency divider with transconductance boosting technique

Abomaashzadeh

Nabavi

Saeedi

2018

This paper presents a degenerated injector (mixer) with transconductance boosted by biasing the mixer transistor in the knee region of its I-V curve, without increasing the transistor size and its parasitics. This mixer can enhance the locking range of millimeter-wave injection-locked frequency dividers. To compensate the degradation of mixer transconductance (conversion-gain) due to the degeneration effect, a neutralization technique is employed. Analyses are given for locking-range and induced phase-noise of the proposed divider for arbitrary injection strength. It is shown that the locking-range, as a function of injection strength, is improved by increasing the fundamental component of transconductance. Using 180-nm CMOS technology, a 1.78-mW divider-bytwo is designed with free-running frequency of 27.92 GHz, locking-range of 51 to 59.6 GHz, and figure-of-merit of 4.83 (GHz/mW). EM simulation results of the proposed and conventional structure are compared, which illustrates 56% improvement in locking-range.