Dithering Skip Modulation, Width and Dead Time Controllers in Highly Efficient DC-DC Converters for System-On-Chip Applications

Abstract

This paper proposes temperature-independent load sensor (LS), optimum width controller (OWC), optimum deadtime controller (ODC), and tri-mode operation to achieve high efficiency over an ultra-wide-load range. Higher power efficiency and wider loading current range require rethinking the control method for DC-DC converters. Therefore, a highly efficient tri-mode DC-DC converter is invented in this paper for system-on-chip (SoC) applications, which is switched to sleeping mode at very light load condition or to high-speed mode at heavy load condition. The efficiency improvement is upgraded by inserting new proposed dithering skip modulation (DSM) between conventional pulse-width modulation (PWM) and pulse-frequency modulation (PFM). In other words, an efficiency-improving DSM operation raises the efficiency drop because of transition from PWM to PFM. Importantly, DSM mode can dynamically skip the number of gate driving pulses, which is inverse proportional to load current. Simplistically and qualitatively stated, the novel load sensor automatically selects optimum modulation method and power MOSFET width to achieve high efficiency over a wide load range. Moreover, optimum power MOSFET turn-on and turn-off delays in synchronous rectifiers and reduced ground bounce can save much switching loss by current-mode dead-time controller. Experimental results show the tri-mode operation can have high efficiency about 90% over a wide load current range from 3 to 500 mA. Owing to the effective mitigation of the switching loss contributed by optimum power MOSFET width and reduction of conduction loss contributed by optimum dead-times, the novel width and dead-time controllers achieve high efficiency about 95% at heavy load condition and maintain the highly efficient performance to very light load current about 0.1 mA.

High efficiency DCM buck converter with dynamic logic based adaptive switch-time control

“…Few other dead-time control techniques are reported in [14][15][16]. The DLL based dead-time controller in [14] requires extensive analog components, which are sensitive to noise interference, and are difficult to realise.…”

“…Another sensorless dead-time controller reported in [15] exploits a complex digital algorithm to search the optimal dead time over a long period, and hence is not suitable for power converters for portable applications. Huang et al [16] report a load dependent dead-time controller, which adjusts the dead time according to the load condition. However, it requires an on-chip current sensor and calibration circuits in the controller.…”

Efficient and optimized design of Synchronous buck converter with feedback compensation in 130nm technology

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A reliability improved synchronous boost converter with spike suppression circuit

“…So, a dead-time [2,3] is inserted to the gate control signals. In order to improve the efficiency, various literatures are reported to optimize the dead-time [4,5,6,7,8,9,10]. In [6], the dead time of the power transistors can be dynamically optimized under any load condition.…”