DITES: A Lightweight and Flexible Dual-Core Isolated Trusted Execution SoC Based on RISC-V

Abstract

A Trusted Execution Environment (TEE) is an efficient way to secure information. To obtain higher efficiency, the building of a dual-core system-on-chip (SoC) with TEE security capabilities is the hottest topic. However, TEE SoCs currently commonly use complex processor cores such as Rocket, resulting in high resource usage. More importantly, the cryptographic unit lacks flexibility and ignores secure communication in dual cores. To address the above problems, we propose DITES, a dual-core TEE SoC based on a Reduced Instruction Set Computer-V (RISC-V). At first, we designed a fully isolated multi-level bus architecture based on a lightweight RISC-V processor with an integrated crypto core supporting Secure Hashing Algorithm-1 (SHA1), Advanced Encryption Standard (AES), and Rivest–Shamir–Adleman (RSA), among which RSA can be configured to five key lengths. Then, we designed a secure boot based on Chain-of-Trust (CoT). Furthermore, we propose a hierarchical access policy to improve the security of inter-core communication. Finally, DITES is deployed on a Kintex 7 Field-Programmable-Gate-Array (FPGA) with a power consumption of 0.297 W, synthesized using TSMC 90 nm. From the results, the acceleration ratios of SHA1 and RSA1024 decryption/encryption can reach 75 and 1331/1493, respectively. Compared to exiting TEE SoCs, DITES has lower resource consumption, higher flexibility, and better security.

Design and Implementation of Low-Power IoT RISC-V Processor with Hybrid Encryption Accelerator

“…Table 5 provides an overview of the LUT (lookup table) and FF (flip-flop) resource utilization for the proposed processor, both with and without the hybrid encryption accelerator. In order to facilitate comparisons, we also present the relevant parameters for two other open-source RISC-V IoT processors, namely, the Hummingbird E203 [41] and XuanTie E902 [42], utilizing similar experimental platforms. The Hummingbird E203 processor is a 32-bit RISC-V architecture IP developed by Nuclei Systems Technology for low-power, small-area scenarios.…”