Distributed Virtual Bit-Slice Synchronizer: A Scalable Hardware Barrier Mechanism for n-Dimensional Meshes

Bidirectional Virtual Bit-slice Synchronizer: A Scalable Solution for Hardware-level Barrier Synchronization

“…To guarantee correct operation of the proposed barrier synchronization scheme, a suitable clocking mechanism is required. For this purpose we adopt the Distributed Circulating Wave clocking (DCW-clocking) technique described in paper (Zotov, 2010). However, the usage of the DCW-clocking "as is" isn't possible because of the difference in the control network logic, topology and schemata.…”

“…In the four past decades, there have been developed a wide range of methods for barrier synchronization. Depending on the implementation level existing methods can be divided into three classes: software (Tsafrir and Feitelson, 2002;Li et al, 2004;Tzeng et al, 2005), hybrid (Moh et al, 2001;Hindam, 2004;Sampson et al, 2006) and hardware (Thinking Machines, 1992;Delgado and Kofuji, 1996;Ramakrishnan et al, 1999;Cohen et al, 2000;Johnson and Hoare, 2001;Zotov, 2010;Ashraf et al, 2012;Al-Azzeh, 2013). Hardware barriers have shown to be a better solution in general because they are order-ofmagnitude faster than software methods and produce no extra message traffic compared to hybrid solutions.…”

“…In Zotov (2010), a new hardware-level distributed barrier mechanism for mesh-connected parallel systems has been presented to solve some flexibility issues. This approach, called the Distributed Virtual Bit-Slice Synchronizer (DVBSS), puts away the restrictions on the configuration of barrier groups and, in theory, it eliminates the limitations on the number of barriers in the system.…”

“…In the study, we extend the DVBSS approach presented in Zotov (2010). The objective of the study is to present a modified distributed hardware barrier architecture making it possible to transfer barrier state signals through the mesh in two opposite directions between two corner units thus eliminating the wrap around connections of the DVBSS network and providing better flexibility and scalability.…”

Active memory controller

“…Several recent cluster interconnects support distributed synchronization operations [38,49], e.g., the Quadrics™QsNet interconnect [38] supports both pure hardware barriers and network processor-based hybrid barriers. Zotov [59] supports the barrier operation using a dedicated network. Other researchers have proposed adding specialized vector operations to the memory controller to support vector scatter-add [1] or parallel reduction operations [15].…”