Distributed image processing based on the same IP-cores in FPGA-architecture

Abstract

The problem of processing images, i. e., two-dimensional data arrays, was solved through implementing two-dimensional fast Fourier transform (FFT) when using single-type hardware modules – IP-cores in the Virtex-6 FPGA architecture. We have shown the possibility of the parallel implementation of each stage in the two-dimensional FFT, based on four “butterfly”-type transforms (BTr) over four elements of the data array being processed. Estimations were obtained regarding time- and hardware complexity of the IPcore implementing BTrs and used in implementing the one-dimensional FFT. The results obtained can be used in estimating hardware and time consumption when performing a twodimensional FFT over an array of the pre-defined dimensionality in using existing and forthcoming distributed programmable-architecture systems.