Distortion Contribution Analysis for Identifying EM Immunity Failures

Abstract

where he received the master's degree (cum laude) in electrical engineering in 1997, a qualification to teach physics in 2000, and the Ph.D. degree (cum laude) for his thesis "MOSFET LF noise under large signal excitation" in 2004. He is currently a Team Lead for a group of power conversion specialists at NXP in Eindhoven, The Netherlands. His current research interests include integrated power conversion, LF noise in CMOS technology, clock and data recovery for high speed serial links, and digitally assisted analog circuit design.

A Study on the Frequency-Domain Black-Box Modeling Method for the Nonlinear Behavioral Level Conduction Immunity of Integrated Circuits Based on X-Parameter Theory

“…The accuracy of the mod method is verified by comparing the actual DPI test results of the board. Similarly comparison of the measured and simulated results of the frequency-and time-do measurements at 50 MHz after inputting interference signals with different powers ures[19][20][21][22] shows that the jitter of the chip's output response increases as the input p is increased. When the input power is 10 dBM, the output signal is severely distorted the chip cannot work properly.…”

“…In general, chips exhibit nonlinearity when sensitized by conducted interference [19], and this nonlinear effect is the main cause of EMC failures on chips. This is why the assumption of linearity often leads to biased final predictions [20,21]. When a small signal is injected, at this moment, the system exhibits linear characteristics and the harmonic frequencies at the output are negligible.…”

“…By using an RF generator, RF amplifiers, directional coupler, bias-tees, RF power ters, oscilloscopes, and other equipment, the interference waveforms specifie IEC62132-1 are applied to the chip, and the output waveforms of the chip are recor DPI measurements are performed by injecting an interference signal into the DUT (o V+ pin or input) via a bias tee, with the operational amplifier used as a follower ci and powered by a supply voltage of ±3 V. The V+ pin is set to 0 VDC. [19][20][21][22] shows that the jitter of the chip's output response increases as the input p is increased. When the input power is 10 dBM, the output signal is severely distorted the chip cannot work properly.…”