2010
DOI: 10.1063/1.3522651
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Distinguishing impurity concentrations in GaAs and AlGaAs using very shallow undoped heterostructures

Abstract: We demonstrate a method of making a very shallow, gateable, undoped 2-dimensional electron gas. We have developed a method of making very low resistivity contacts to these structures and systematically studied the evolution of the mobility as a function of the depth of the 2DEG (from 300nm to 30nm). We demonstrate a way of extracting quantitative information about the background impurity concentration in GaAs and AlGaAs, the interface roughness and the charge in the surface states from the data. This informati… Show more

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Cited by 31 publications
(63 citation statements)
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“…We observe gate hysteresis in electron devices at 130 K very similar to that in hole devices at T < 4 K. We also show that the hysteresis can be reduced in hole devices by reducing the thickness of the dopant layer from 80 nm to less than 5 nm (δ-doped). Overall, our results point to competition between surface-state and dopant related processes with different time/energy scales as the cause of the hysteresis, and have wider implications given recent interest in surface charge as a source of scattering 38 and dopant charge migration as a source of noise 39 in AlGaAs/GaAs heterostructures and quantum devices.…”
mentioning
confidence: 95%
“…We observe gate hysteresis in electron devices at 130 K very similar to that in hole devices at T < 4 K. We also show that the hysteresis can be reduced in hole devices by reducing the thickness of the dopant layer from 80 nm to less than 5 nm (δ-doped). Overall, our results point to competition between surface-state and dopant related processes with different time/energy scales as the cause of the hysteresis, and have wider implications given recent interest in surface charge as a source of scattering 38 and dopant charge migration as a source of noise 39 in AlGaAs/GaAs heterostructures and quantum devices.…”
mentioning
confidence: 95%
“…Nevertheless, the requirement that the gate electrode overlaps the rough annealed ohmic metal enhances the possibility of undesired leakage paths [27,28]. In general, the absence of dopants makes fabrication of reliable ohmic contacts with high yield and low contact resistance challenging [20,28] in completely undoped structures.…”
mentioning
confidence: 99%
“…Device yield is often low and the devices can suffer from high contact resistance. Another FET design reported in the literature utilizes a lithographically-defined global top-gate deposited on top of insulators such as polyimides [17,[19][20]23], nitrides [24,25] or oxides [26] separating the ohmic contacts from the gate. In this configuration the global top-gate must extend over the ohmic contact pad to ensure a continuous 2DEG to the ohmic contact.…”
mentioning
confidence: 99%
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