Distinctly different thermal decomposition pathways of ultrathin oxide layer on Ge and Si surfaces

Prabhakaran, K.; Maeda, Fumihiko; Watanabe, Yoshio; Ogino, T.

doi:10.1063/1.126309

Cited by 276 publications

(193 citation statements)

References 16 publications

Supporting

Mentioning

181

Contrasting

Unclassified

Order By: Relevance

“…This occurs at 400°C for ozone oxidation of Ge. At higher temperatures, transformation of GeO 2 (4+ state) to GeO (2+) state occurs at the interface [12], GeO 2 + Ge → 2 GeO which causes increase in D it (Fig 2, for 450°C A new technique to passivate the interface of Ge using thermal oxidation in ozone prior to a dielectric deposition has been developed to improve CMOS performance. D it distributions over the bandgap and close to band edges were extracted using conductance technique at low temperatures to avoid short time constants for capture and emission processes of carriers through interface traps due to smaller bandgap of Ge.…”

Section: Resultsmentioning

confidence: 99%

Ge-Interface Engineering With Ozone Oxidation for Low Interface-State Density

Kuzum

Krishnamohan

Pethe

et al. 2008

IEEE Electron Device Lett.

186

107

View full text Add to dashboard Cite

Abstract-Passivation of Ge has been a critical issue for Ge MOS applications in future technology nodes. In this letter, we introduce ozone-oxidation to engineer Ge/insulator interface. Interface states (D it ) values across the bandgap and close to conduction bandedge were extracted using conductance technique at low temperatures. D it dependency on growth conditions was studied. Minimum D it of of 3x10 11 cm -2 V -1 was demonstrated. Physical quality of the interface was investigated through Ge 3d spectra measurements. We found that the interface and D it is strongly affected by the distribution of oxidation states and quality of the suboxide.

show abstract

Section: Resultsmentioning

confidence: 99%

Ge-Interface Engineering With Ozone Oxidation for Low Interface-State Density

Kuzum

Krishnamohan

Pethe

et al. 2008

IEEE Electron Device Lett.

186

107

View full text Add to dashboard Cite

show abstract

“…Sequentially, poor interface properties and high gate leakage current will be exhibited in the Ge-MOS device. [3][4][5][6][7] Various pre-gate surface modification techniques, such as surface nitridation or Si passivation, have been developed to improve the quality of gate insulator/Ge interface. 13 It was also reported that high-performance Ge MOSFET could be realized by careful control of interfacial GeO 2 formation.…”

mentioning

confidence: 99%

Effects of postgate dielectric treatment on germanium-based metal-oxide-semiconductor device by supercritical fluid technology

Liu

Huang

et al. 2010

Applied Physics Letters

View full text Add to dashboard Cite

Supercritical fluid ͑SCF͒ technology is employed at low temperature as a postgate dielectric treatment to improve gate SiO 2 /germanium ͑Ge͒ interface in a Ge-based metal-oxide-semiconductor ͑Ge-MOS͒ device. The SCF can transport the oxidant and penetrate the gate oxide layer for the oxidation of SiO 2 / Ge interface at 150°C. A smooth interfacial GeO 2 layer between gate SiO 2 and Ge is thereby formed after SCF treatment, and the frequency dispersion of capacitance-voltage characteristics is also effectively alleviated. Furthermore, the electrical degradation of Ge-MOS after a postgate dielectric annealing at 450°C can be restored to a extent similar to the initial state.

show abstract

“…At 500°C, most of the Ge oxides were desorbed through an interfacial reaction of GeO 2 +Ge+2GeO between the native oxide layer and the Ge substrate. This is then followed by desorption of volatile GeO from the surface, with it being reported in the literature that GeO sublimates at low temperature [19,20]. Secondary ion mass spectroscopy (SIMS) profiles confirm the loss of 100 nm from the Ge layer at 600°C.…”

Section: Annealing Of the Ge Nanostructuresmentioning

confidence: 84%

Annealing study of two-dimensional patterned Ge nanostructures via nanosphere lithography

et al. 2011

View full text Add to dashboard Cite

Abstract:Experimental studies on patterning hexagonal Ge nanostructures have been conducted on Si substrates through deposition of Ge with colloidal particles as a mask. The deposited Ge thin film possesses, according to the X-ray diffraction measurements, in plane texture, being epitaxial and aligned with the (111) Si substrate. The size distribution of the patterned Ge nanostructures is narrow, as indicated by the atomic force microscopy and scanning electron microscopy measurements. We have obtained Ge nanostructures with lateral dimension of 490 nm (height 12 nm), 200 nm (height 6 nm) and 82 nm (height 6 nm) by using different sizes of polystyrene spheres. We have performed in depth studies of the Ge nanostructures' behavior due to thermal and rapid thermal post-annealing processes. FT micro-Raman spectroscopy shows that there is no Si intermixing during the annealing process. In order to quantify the changes in the height and lateral dimension, we have performed atomic force microscopy and white light interferometry analysis. The changes in shape and the decrease in the area of a cross-section of Ge nanostructure will be discussed in respect to similar results shown in the literature for Ge thin films during the annealing process.

show abstract

Distinctly different thermal decomposition pathways of ultrathin oxide layer on Ge and Si surfaces

Cited by 276 publications

References 16 publications

Ge-Interface Engineering With Ozone Oxidation for Low Interface-State Density

Ge-Interface Engineering With Ozone Oxidation for Low Interface-State Density

Effects of postgate dielectric treatment on germanium-based metal-oxide-semiconductor device by supercritical fluid technology

Annealing study of two-dimensional patterned Ge nanostructures via nanosphere lithography

Contact Info

Product

Resources

About