Dispersive readout of a silicon quantum dot with an accumulation-mode gate sensor

Abstract

Sensitive charge detection has enabled qubit readout in solid-state systems. Recently, an alternative to the well-established charge detection via on-chip electrometers has emerged, based on in situ gate detectors and radio-frequency dispersive readout techniques. This approach promises to facilitate scalability by removing the need for additional device components devoted to sensing. Here, we perform gate-based dispersive readout of an accumulation-mode silicon quantum dot. We observe that the response of an accumulation-mode gate detector is significantly affected by its bias voltage, particularly if this exceeds the threshold for electron accumulation. We discuss and explain these results in light of the competing capacitive contributions to the dispersive response.Reliable measurements of the charge state of nanoscale electronic devices may represent a key ingredient for the realization of future quantum technologies. Typically, non-invasive and sensitive charge readout is achieved by means of on-chip electrometers 1,2 . The scope of applicability of these sensing techniques is quite broad, ranging from charge noise characterization 3-5 to cryogenic thermometry 6-8 , as well as Maxwell's demon implementations 9,10 and quantum metrology 11-13 . Arguably, one of the research fields that has more largely benefitted from advancements in charge sensing is solid-state quantum information processing [14][15][16][17][18] .Recently, an alternative approach to implement charge readout has emerged based on radio-frequency (rf) resonant circuit techniques [19][20][21] . Using in-situ gate electrodes embedded into LC resonators, fast and sensitive charge detection has been attained 22-25 by measuring the dispersive shift of the resonator frequency when electron tunneling occurs. In addition to providing much higher bandwidth than standard electrometry, gate-based reflectometry has an enormous potential for realizing scalable quantum architectures. In fact, a number of proposals has been already put forward to exploit high frequency techniques to different extents [26][27][28][29][30][31] .Lately, spin-based qubits have been realised in planar silicon-based accumulation-mode quantum dots 18,32,33 . Gate-based dispersive readout may be an appealing technique to scale these systems up.In fact, CMOS-compatible architectures have been recently proposed 27,28 which identify routes toward large scalability of silicon-based spin qubit systems. The suggested readout protocol crucially relies on the gate-based dispersive technique discussed here. It has, therefore, become topical to understand its operational boundaries or limitations. In the specific case of accumulation-mode devices, it has been proposed that the same gate(s) used to define the qubit(s) may be used for dispersive readout 26,27 . This would require operating the gate(s) above threshold voltage. However, one has to be aware that the gate capacitance may significantly vary upon bias voltage and, in some circumstances, its contribution may dominate over the tunnelin...

Gate-based single-shot readout of spins in silicon

“…Alternatively, the spin state can be measured directly by detecting the complex impedance of spin-dependent electron tunnelling between quantum dots [9][10][11]. This can be achieved using radio-frequency reflectometry on a single gate electrode defining the quantum dot itself [11][12][13][14][15], significantly reducing gate count and architectural complexity, but thus far it has not been possible to achieve single-shot spin readout using this technique. Here, we detect single electron tunnelling in a double quantum dot and demonstrate that gate-based sensing can be used to read out the electron spin state in a single shot, with an average readout fidelity of 73%.…”

“…Building on previous work in this system [14], we optimise the gate design for dispersive sensing by removing the possibility for electrons to accumulate under G 1 ,G 2 in the fan-out region of the device. Such electrons induce a gate-voltage dependent contribution to C p , even if they are far away from the quantum dot [14,26] and interfere with the gate-based sensing. By extending gate C to this region, we prevent electron accumulation under G 1 ,G 2 .…”

A CMOS dynamic random access architecture for radio-frequency readout of quantum devices

“…We can identify three regions: The on region for V WLi > 0.9 V, where we observe single electron tunneling, the off region for V WLi < 0.7 V, where we observe no transitions and finally, for 0.7 V< V WLi < 0.9 V the forbidden region. In the latter, T i is in the saturation regime, where, due to the voltage-dependence gate capacitance of the control FET, the phase varies largely [43]. This region should be avoided when assigning voltage levels.…”

Fan-out Estimation in Spin-based Quantum Computer Scale-up

“…By adding interconnects between qubits, we have some flexibility in arranging the qubits and thus can analyse the fanout scalability accordingly. Secondly, we assume each qubit in the array has its own spin read-out device which is usually a Single Electron Transistor (SET 37 ) or equivalent 38 – 42 . This assumption may appear to be more than necessary since neighboring qubits can share a common readout device by using some forms of readout multiplexing, for example, the schemes presented in ref.…”