Disaggregated memory for expansion and sharing in blade servers

Abstract

Analysis of technology and application trends reveals a growing imbalance in the peak compute-to-memory-capacity ratio for future servers. At the same time, the fraction contributed by memory systems to total datacenter costs and power consumption during typical usage is increasing. In response to these trends, this paper reexamines traditional compute-memory co-location on a single system and details the design of a new general-purpose architectural building block-a memory blade-that allows memory to be "disaggregated" across a system ensemble. This remote memory blade can be used for memory capacity expansion to improve performance and for sharing memory across servers to reduce provisioning and power costs. We use this memory blade building block to propose two new system architecture solutions-(1) page-swapped remote memory at the virtualization layer, and (2) block-access remote memory with support in the coherence hardware-that enable transparent memory expansion and sharing on commodity-based systems. Using simulations of a mix of enterprise benchmarks supplemented with traces from live datacenters, we demonstrate that memory disaggregation can provide substantial performance benefits (on average 10X) in memory constrained environments, while the sharing enabled by our solutions can improve performance-per-dollar by up to 87% when optimizing memory provisioning across multiple servers.

Barely Alive Servers: Greener Datacenters Through Memory-Accessible, Low-Power States

“…Another approach that enables remote memory accesses in a blade chassis is disaggregated memory (DM) [Lim et al(2009)]. In DM, a set of memory blades extend the memory of the compute blades.…”

PARS: A scheduling of periodically active rank to optimize power efficiency for main memory

“…However, as processors have become more energy-efficient and more effective at managing their own power consumption, their contribution has been decreasing. In contrast, main memory energy consumption has been growing (Barroso and Hölzle, 2009;Lefurgy et al, 2003;Lim et al, 2009;Deng et al, 2011), as multi-core systems are requiring increasing main memory bandwidth and capacity. Making matters worse, memory energy management is challenging in the context of servers with modern (DDRn) DRAM technologies.…”

Switching Optically-Connected Memories in a Large-Scale System

“…With the continual increase in the number of central processing unit (CPU) cores within a chip, the increased processing capacity per socket demands increase in memory size to support increased OS footprint, high data volume, increased number of virtual machines (VMs), etc. Projections on the rate of growth of per-socket memory capacity reveal that the supply of memory capacity fails to remain at par with the demand [1], [2]. Also, tight coupling (co-location) of memory modules with CPUcores through the system bus precludes a few performance optimizations, for example, memory consolidation among a group of servers (processors) and decoupling processor and memory failures.…”

“…Also, tight coupling (co-location) of memory modules with CPUcores through the system bus precludes a few performance optimizations, for example, memory consolidation among a group of servers (processors) and decoupling processor and memory failures. Recent studies reveal that provisioning processors with the worst-case memory requirements leads to underutilization of the resources due to temporal variations in various system states, for example, I/O and application workloads or traffic patterns, data access patterns, and working set characteristics [3], [4], [1]. Thus, a new architectural mechanism to allow transparent memory ‡ The research work was done while the first author was working at IBM T.J. Watson Research Center, NY, USA as a post-doctoral researcher.…”

“…Though such a system results in an increased memory latency, experimental works show the impact of the increased latencies on application performance negligible [1], [8]. Lim et al [1] propose an architecture segregating memory from the processors and propose techniques to access remote memories; the authors show 10x performance benefit emanating from such a memory segregation.…”