Proceedings of the 2018 International Conference on Supercomputing 2018
DOI: 10.1145/3205289.3205324
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Directive-Based, High-Level Programming and Optimizations for High-Performance Computing with FPGAs

Abstract: Reconfigurable architectures like Field Programmable Gate Arrays (FPGAs) have been used for accelerating computations from several domains because of their unique combination of flexibility, performance, and power efficiency. However, FPGAs have not been widely used for high-performance computing, primarily because of their programming complexity and difficulties in optimizing performance. In this paper, we present a directive-based, high-level optimization framework for high-performance computing with FP-GAs,… Show more

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Cited by 8 publications
(2 citation statements)
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References 21 publications
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“…The kernel generated from the annotated region is already optimized. A follow-up publication [Lambert et al 2018], by the same group, adds new optimizations to the compiler. Unlike the work of Lloyd et al, the solution does not require host and device compiler integration because the compiler has control of the device code that is produced.…”
Section: Background and Related Workmentioning
confidence: 99%
“…The kernel generated from the annotated region is already optimized. A follow-up publication [Lambert et al 2018], by the same group, adds new optimizations to the compiler. Unlike the work of Lloyd et al, the solution does not require host and device compiler integration because the compiler has control of the device code that is produced.…”
Section: Background and Related Workmentioning
confidence: 99%
“…As a result, hardware accelerators such as GPUs, FPGAs, and customized ASICs have been employed to accelerate DNNs [4], [5], [6], [7], [8], [9], [10], [11]. Among them, FPGAs emerges as a promising solution owing to its high available parallelism and flexibility [12], [13], [14], [15], [16], [17].…”
Section: Introductionmentioning
confidence: 99%