Directed self-assembly (DSA) grapho-epitaxy template generation with immersion lithography

Ma, Yuling; Lei, Junjiang; Torres, J. Andres; Li, Hong; Word, James; Fenger, Germain; Tritchkov, Alexander; Lippincott, George; Gupta, Rachit; Lafferty, Neal; He, Yuan; Bekaert, Joost; Vanderberghe, Geert

doi:10.1117/12.2085850

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Cited by 5 publications

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“…Directed self-assembly (DSA) is gaining strong interests from academia and industry to improve both throughput and resolution, thus it is a potential candidate for sub-7nm technology nodes [79][80][81]. Selfassembly is a process that block copolymer (BCP) forms organized nanoscale structures.…”

Section: Mpl Layout Decompositionmentioning

confidence: 99%

Design for manufacturability and reliability in extreme-scaling VLSI

Roy

et al. 2016

Sci. China Inf. Sci.

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In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore's law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI.

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Section: Mpl Layout Decompositionmentioning

confidence: 99%