Direct Transistor-level Layout for Digital Blocks

Gopalakrishnan, Prakash; Rutenbar, Rob A.

doi:10.1007/b117054

2005

DOI: 10.1007/b117054

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Direct Transistor-level Layout for Digital Blocks

Prakash Gopalakrishnan

Rob A. Rutenbar

Abstract: Chapter 3 Global Placement 35 Chapter 4 Detailed Placement And Layout Results 49 vi Direct Transistor-Level Layout for Digital Blocks 75 77 78 79 80 81 85 88 89 90 91 91 92 95 96 97 101 Chapter 5 Timing-Driven Placement 77 Chapter 6 Conclusion 103 Appendix 107 Bibliography 115 Index 123 Contents vii PRAKASH GOPALAKRISHNAN NEOLINEAR, INC.

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A novel synthesis strategy driven by partial evaluation based circuit reduction for application specific DSP circuits

Mukherjee

Vemuri

Proceedings 21st International Conference on Computer Design

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Traditional application specific synthesis systems for DSP rely on a predesigned library of components. Designs in the DSP domain often involve constant operands. Using off-the-shelf library components for such designs can be wasteful in terms of area, power and timing. Operations involving constant operands are possible candidates for reduction based on partial evaluation. Classical logic synthesis is often incapable of performing reductions because of component sharing (typically decided during high level synthesis) between regular operations and those involving constant operands, which prevent minimizations during this phase. In this paper we propose a methodology for performing on-demand component reduction using partial evaluation during synthesis of application specific DSP circuits. The simplified components have better characteristics compared to their unreduced counterparts in terms of both delay and power. Use of reduced components in the synthesis loop showed a system wide improvement in performance, area and power for the synthesized designs for a variety of benchmark DSP circuits.

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A novel synthesis strategy driven by partial evaluation based circuit reduction for application specific DSP circuits

Mukherjee

Vemuri

Proceedings 21st International Conference on Computer Design

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A multiple-row transistor placement system for full custom design

Chou¹,

Chen²,

Yang³

et al.

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).

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Direct Transistor-level Layout for Digital Blocks

Cited by 2 publications

References 24 publications

A novel synthesis strategy driven by partial evaluation based circuit reduction for application specific DSP circuits

A novel synthesis strategy driven by partial evaluation based circuit reduction for application specific DSP circuits

A multiple-row transistor placement system for full custom design

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