2009
DOI: 10.1016/j.jfranklin.2008.06.004
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Direct synthesis-based controller design for integrating processes with time delay

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Cited by 117 publications
(32 citation statements)
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“…The performance comparison of the proposed controller with the PID controllers designed by recently reported methods (Seshagiri Rao and Chidambaram [30], Seshagiri Rao et al [24], Chidambaram and Padma Sree [29], Anil and Padma Sree [28] …”
Section: Simulation Resultsmentioning
confidence: 99%
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“…The performance comparison of the proposed controller with the PID controllers designed by recently reported methods (Seshagiri Rao and Chidambaram [30], Seshagiri Rao et al [24], Chidambaram and Padma Sree [29], Anil and Padma Sree [28] …”
Section: Simulation Resultsmentioning
confidence: 99%
“…(17a) and Eq. (17b) (Seshagiri Rao et al [24]). The stability regions are tabulated with the IMC-PID controller considering 10% of designed filter time constants in Table 3 along with the stability regions obtained by the IMC-PID controller with the designed filter time constants.…”
Section: Case Studymentioning
confidence: 99%
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