Direct GPU/FPGA communication Via PCI express

Bittner, Ray; Ruf, Erik; Forin, Alessandro

doi:10.1007/s10586-013-0280-9

Cited by 54 publications

(17 citation statements)

References 5 publications

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“…This paper realizes PCI Express interface [3] by using Virtex-6 of Xilinx company. The inside of this chip is integrated with PCIe IP Core [4]. This IP hard core achieves the functions of physical layer, data link layer and part of transaction layer, which enable developers to avoid underlying development.…”

Section: Express Protocol and Data Package Structurementioning

confidence: 99%

The High-speed Interface Design Based on PCIe of the Non-cooperative Receiver Verification Platform

Li¹,

Cheng²,

Qin³

2017

dtetr

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The data transfer rate of the non-cooperate receiver is demanded very high. This paper uses the Xilinx Virtex-6 Series board as the hardware platform to transfer data received and through the front-end processing to the PC, and verifies the modulation pattern recognition algorithms. In order to meet the design requirements, we selected PCI Express bus. This paper describes the high-speed interface design, including DMA module design, the driver and the like. After the experiment, the data rate of the system can reach 1633GB/s, fully meet the design requirements. KEYWORD Verification platform; PCIE; DMA GENERAL INSTRUCTIONSNon-cooperative communication has broad application prospects in the field of electronic countermeasure, communication information interception, civil communication monitoring, spectrum management, etc.. For receiver terminal, the modulation mode adopted by the sending terminal is unknown, the modulation parameter estimation becomes the premise of the correct analysis of the information. All the commonly used modulation parameter estimation algorithms, such as higherorder cumulant and cyclic spectrum, etc. need very great operand amount and complex mathematical operations. This becomes the bottleneck of implementation of non-cooperative receiver FGPA. With the increase of PCIe bus throughput rate and FPGA processing capacity, it makes the realization of non-cooperative receiver hardware platform through the adoption of high speed signal processing architecture of FPGA + PC possible.

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Section: Express Protocol and Data Package Structurementioning

confidence: 99%

The High-speed Interface Design Based on PCIe of the Non-cooperative Receiver Verification Platform

Li¹,

Cheng²,

Qin³

2017

dtetr

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“…The direct streaming from a GPU to an FPGA has been demonstrated. 34 Alternatively, the field of HPC on FPGAs, whilst still in its infancy, is gaining in popularity and this provides potential for reaching the real-time data processing scale for SAMI. Similar cross-correlation computation has been done on an FPGA for a passive millimetre wave aperture synthesis imager 35 so there is potential the SAMI data processing could be done on FPGA technology.…”

Section: 33mentioning

confidence: 99%

GPU-Based Data Processing for 2-D Microwave Imaging on MAST

Chorley

Akers

Brunner

et al. 2016

Fusion Science and Technology

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“…Some authors investigated the direct communication between FPGAs and Graphics Processing Units (GPUs) using PCIe [23,24]. These approaches will be useful for implementing scenario (C) from Fig.…”

Section: Related Workmentioning

confidence: 99%