Dip: A parallel program development environment

Labarta, Jesús; Girona, S.; Pillet, Vincent; Cortes, Toni; Gregoris, Luis

doi:10.1007/bfb0024763

Cited by 133 publications

(92 citation statements)

References 13 publications

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“…We used PAR-AVER [20], a visualization and performance analysis tool developed at CEPBA, to collect data and statistics and to show the trace of each process during the tests.…”

Section: Resultsmentioning

confidence: 99%

Balancing HPC applications through smart allocation of resources in MT processors

Boneti

Gioiosa

Cazorla

et al. 2008

2008 IEEE International Symposium on Parallel and Distributed Processing

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Abstract-Many studies have shown that load imbalancing causes significant performance degradation in High Performance Computing (HPC) applications. Nowadays, Multi-Threaded (MT 1 ) processors are widely used in HPC for their good performance/energy consumption and performance/cost ratios achieved sharing internal resources, like the instruction window or the physical register. Some of these processors provide the software hardware mechanisms for controlling the allocation of processor's internal resources. In this paper, we show, for the first time, that by appropriately using these mechanisms, we are able to control the tasks speed, reducing the imbalance in parallel applications transparently to the user and, hence, reducing the total execution time. Our results show that our proposal leads to a performance improvement up to 18% for one of the NAS benchmark. For a real HPC application (much more dynamic than the benchmark) the performance improvement is 8.1%. Our results also show that, if resource allocation is not used properly, the imbalance of applications is worsened causing performance loss.

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“…We used PAR-AVER [20], a visualization and performance analysis tool developed at CEPBA, to collect data and statistics and to show the trace of each process during the tests.…”

Section: Resultsmentioning

confidence: 99%

Balancing HPC applications through smart allocation of resources in MT processors

Boneti

Gioiosa

Cazorla

et al. 2008

2008 IEEE International Symposium on Parallel and Distributed Processing

Self Cite

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“…The tools Paraver and Dimemas [11] developed by the Barcelona Supercomputing Center provide interactive event trace visualization and trace-based replay. They allow performance analysis as well as simulation of parallel run-time behaviour under altered conditions.…”

Section: Background and Related Workmentioning

confidence: 99%

Score-P: A Unified Performance Measurement System for Petascale Applications

Mey

Biersdorf

Bischof

et al. 2011

Competence in High Performance Computing 2010

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The rapidly growing number of cores on modern supercomputers imposes scalability demands not only on applications but also on the software tools needed for their development. At the same time, increasing application and system complexity makes the optimization of parallel codes more difficult, creating a need for scalable performance-analysis technology with advanced functionality. However, delivering such an expensive technology can hardly be accomplished by single tool developers and requires higher degrees of collaboration within the HPC community. The unified performance-measurement system Score-P is a joint effort of several academic performance-tool builders, funded under the BMBF program HPC-Software für skalierbare Parallelrechner in the SILC project (Skalierbare Infrastruktur zur automatischen Leistungsanalyse paralleler Codes). It is being developed with the objective of creating a common basis for several complementary optimization tools in the service of enhanced scalability, improved interoperability, and reduced maintenance cost.

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“…However, a wide number of papers deals with parallel and distributed system modeling and performance analysis [17][18], and it is likely that many existing simulation environments and tools could be applied to carry out performance analyses similar to those that are the object of this paper. Other authors focus their interest in tools for performance-driven software development, mainly in the context of Performance Engineering (see per example [19][20]).…”

Section: Related Workmentioning

confidence: 99%

Off-Line Performance Prediction of Message-Passing Applications on Cluster Systems

Mancini

Rak

Torella

et al. 2003

Recent Advances in Parallel Virtual Machine and Message Passing Interface

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Abstract. This paper describes a simulation-based technique for the performance prediction of message-passing applications on cluster systems. Given data measuring the performance of a target cluster in the form of standard benchmark results, along with the details of the chosen computing configuration (e.g., the number of nodes), it is possible to build and to validate automatically a detailed simulation model. This makes it possible to predict the performance of fully-developed or skeletal code off-line, i.e., without resorting to the real hardware. The reasonable accuracy obtained makes this approach particularly useful for preliminary performance testing of parallel code on non-available hardware. After a description of the approach and of the construction and validation of the simulation model, the paper presents a case study.

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Dip: A parallel program development environment

Cited by 133 publications

References 13 publications

Balancing HPC applications through smart allocation of resources in MT processors

Balancing HPC applications through smart allocation of resources in MT processors

Score-P: A Unified Performance Measurement System for Petascale Applications

Off-Line Performance Prediction of Message-Passing Applications on Cluster Systems

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